Testing of Neuromorphic Circuits: Structural vs Functional

Gebregiorgis, Anteneh; Tahoori, Mehdi B.

doi:10.1109/itc44170.2019.9000110

Cited by 29 publications

(8 citation statements)

References 27 publications

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“…With the widespread use of NN/CNN and the rise of AI accelerators, the testing of these hardware has become an emerging research problem [32]- [34]. In [32], a comprehensive structural test flow was proposed that first identified critical faults by comparing the accuracies of the exact fault-free gate-level circuit of the neural network, and that of a faulty version. Next, the entire circuit was converted into an Boolean satisfiability (SAT) instance and solved with SAT solver with test patterns for the critical faults only.…”

Section: A Related Workmentioning

confidence: 99%

“…Next, the entire circuit was converted into an Boolean satisfiability (SAT) instance and solved with SAT solver with test patterns for the critical faults only. Since this approach is expensive and not scalable, a functional test method was proposed [32], where real workloads -the test images from MNIST and CIFAR10 benchmarks -are applied as test input to the gate-level netlist of the implemented neural network. To find if a fault was critical or ignorable, the fault was first injected into a neuron module and the test image set was applied.…”

Section: A Related Workmentioning

confidence: 99%

“…If the prediction accuracy of the test image set was within a certain threshold, the fault was considered unimportant, otherwise, it was a critical fault. The proposed simple approach of creating RTL of the full neural network, followed by gate-level synthesis and fault injection may be applicable for the basic neural networks classifying images with at most 10 possible classes (MNIST and CIFAR10 as used in [32]), however, this approach will not be scalable for mainstream CNNs [39] such as AlexNet, VGG, ResNet, MobileNet, etc. that are used for real-world computer vision tasks of image recognition with many classes [1] [2].…”

Section: A Related Workmentioning

confidence: 99%

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Test and Yield Loss Reduction of AI and Deep Learning Accelerators

Sadi

Guin

2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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With data-driven analytics becoming mainstream, the global demand for dedicated AI and Deep Learning accelerator chips is soaring. These accelerators, designed with densely packed Processing Elements (PE), are especially vulnerable to the manufacturing defects and functional faults common in the advanced semiconductor process nodes resulting in significant yield loss. In this work, we demonstrate an application-driven methodology to reduce the yield loss of AI accelerators by correlating the circuit faults in the PEs of the accelerator with the desired accuracy of the AI workload execution. We exploit the error-healing properties of backpropagation during training, and the inherent fault tolerance features of trained deep learning models during inference to develop the presented yield loss reduction and test methodology. An analytical relationship is derived between fault location, fault rate, and the AI task's accuracy for deciding if the accelerator chip can pass the final yield test. An yield-loss reduction aware fault isolation, ATPG, and test flow are presented for the multiply and accumulate units of the PEs. Results obtained with widely used AI/deep learning benchmarks demonstrate the efficacy of the proposed approach in the reduction of yield loss of AI accelerator designs while maintaining the desired accuracy of AI tasks.

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Section: A Related Workmentioning

confidence: 99%

Section: A Related Workmentioning

confidence: 99%

Section: A Related Workmentioning

confidence: 99%

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Test and Yield Loss Reduction of AI and Deep Learning Accelerators

Sadi

Guin

2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…On-die neural networks have been explored in the past for building an on-die "test brain" that classifies chips as functional or faulty [1]. The "inverse" problem, i.e., how to efficiently test AI hardware accelerators, however, is an emerging problem [2]- [4].…”

Section: Introductionmentioning

confidence: 99%

“…This is expected based on the analogy with biological neural networks which have remarkable fault tolerance capabilities. Some faults, though, are still critical and evidently impact the performance, and test efforts can focus on these critical faults to reduce test time [4].…”

Section: Introductionmentioning

confidence: 99%

Compact Functional Testing for Neuromorphic Computing Circuits

El-Sayed

Spyrou

Camuñas-Mesa

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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We address the problem of testing Artificial Intelligence (AI) hardware accelerators implementing Spiking Neural Networks (SNNs). We define a metric to quickly rank available samples for training and testing based on their fault detection capability. The metric measures the inter-class spike count difference of a sample for the fault-free design. In particular, each sample is assigned a score equal to the spike count difference between the first two top classes. The hypothesis is that samples with small scores achieve high fault coverage because they are prone to misclassification, i.e., a small perturbation in the network due to a fault will result in these samples being misclassififed with high probability. We show that the proposed metric correlates with the per-sample fault coverage and that retaining a set of high-ranked samples in the order of ten achieves near perfect fault coverage for critical faults that affect the SNN accuracy. The proposed test generation approach is demonstrated on two SNNs modelled in Python and on actual neuromorphic hardware. We discuss fault modeling and perform an analysis to reduce the fault space so as to speed up test generation time.

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