Testing reliability techniques for SoCs with fault tolerant CGRA by using live FPGA fault injection

Kuuhn, Johannes Maximilian; Schweizer, T.; Peterson, Dustin; Kuhn, Tommy

doi:10.1109/fpt.2013.6718415

Cited by 6 publications

(2 citation statements)

References 10 publications

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“…Up to two orders of magnitude have been observed between simulation and the proposed solution. Kuuhn et al [19] in 2013 presented a similar approach, but instead of using the JBits API, a tool was developed to make the link. The developed tool provides the correlation between the fault selected at circuit description-for example, VHDL, Verilog-level, and the generated bitstream for the injection of the fault.…”

Section: Fpga-based Acceleration Via Reconfigurationmentioning

confidence: 99%

Enabling ISO 26262 Compliance with Accelerated Diagnostic Coverage Assessment

2020

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Modern vehicles are integrating a growing number of electronics to provide a safer experience for the driver. Therefore, safety is a non-negotiable requirement that must be considered through the vehicle development process. The ISO 26262 standard provides guidance to ensure that such requirements are implemented. Fault injection is highly recommended for the functional verification of safety mechanisms or to evaluate their diagnostic coverage capability. An exhaustive analysis is not required, but evidence of best effort through the diagnostic coverage assessment needs to be provided when performing quantitative evaluation of hardware architectural metrics. These metrics support that the automotive safety integrity level—ranging from A (lowest) to D (strictest) levels—was obeyed. In this context, this paper proposed a verification solution in order to build an approach that can accelerate the diagnostic coverage assessment via fault injection in the semiconductor level (i.e., hardware description language). The proposed solution does not require any modification of the design model to enable acceleration. Small parts of the OpenRISC architecture (namely a carry adder, the Tick Timer peripheral, and the exception block) were used to illustrate the methodology.

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Section: Fpga-based Acceleration Via Reconfigurationmentioning

confidence: 99%

Enabling ISO 26262 Compliance with Accelerated Diagnostic Coverage Assessment

2020

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“…This fault emulation tool inserted faults by manipulating the configuration files. In [32] the authors use a Java library called Static Mapping Library (SML) to do fault emulation. SML allows for small design changes by translating fault locations into the circuit design.…”

Section: A Software-based Techniquesmentioning

confidence: 99%

Validation Techniques for Fault Emulation of SRAM-based FPGAs

Quinn

Wirthlin

2015

IEEE Trans. Nucl. Sci.

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A variety of fault emulation systems have been created to study the effect of single-event effects (SEEs) in static random access memory (SRAM) based field-programmable gate arrays (FPGAs). These systems are useful for augmenting radiation-hardness assurance (RHA) methodologies for verifying the effectiveness for mitigation techniques; understanding error signatures and failure modes in FPGAs; and failure rate estimation. For radiation effects researchers, it is important that these systems properly emulate how SEEs manifest in FPGAs. If the fault emulation systems does not mimic the radiation environment, the system will generate erroneous data and incorrect predictions of behavior of the FPGA in a radiation environment. Validation determines whether the emulated faults are reasonable analogs to the radiation-induced faults. In this paper we present methods for validating fault emulation systems and provide several examples of validated FPGA fault emulation systems.

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RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience

Herkersdorf

Engel

Glaß

et al. 2020

Dependable Embedded Systems

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The Resilience Articulation Point (RAP) model aims to provision a probabilistic fault abstraction and error propagation concept for various forms of variability related faults in deep sub-micron CMOS technologies at the semiconductor material or device levels. RAP assumes that each of such physical faults will eventually manifest as a single- or multi-bit binary signal inversion or out-of-specification delay in a signal transition between bit values. When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, finite state machine (FSM) states, IP macro-interfaces, or software variables. Thus, design concerns can be investigated at higher abstraction layers without the necessity to further consider the full details of lower levels of design. This chapter introduces the ideas of RAP based on examples of particle strike, noise and voltage drop induced bit errors in SRAM cells. Furthermore, we show by different examples how probabilistic bit flips are systematically abstracted and propagated towards instruction and data vulnerability at MPSoC architecture level, and how RAP can be applied for dynamic testing and application-level optimizations in an autonomous robot scenario.

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Testing reliability techniques for SoCs with fault tolerant CGRA by using live FPGA fault injection

Cited by 6 publications

References 10 publications

Enabling ISO 26262 Compliance with Accelerated Diagnostic Coverage Assessment

Enabling ISO 26262 Compliance with Accelerated Diagnostic Coverage Assessment

Validation Techniques for Fault Emulation of SRAM-based FPGAs

RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience

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