Testing SoC interconnects for signal integrity using boundary scan

Abstract

Abstract-As technology shrinks and working frequency reaches the multigigahertz range, designing and testing interconnects are no longer trivial issues. In this paper, we propose an enhanced boundary-scan architecture to test high-speed interconnects for signal integrity. This architecture includes: 1) a modified driving cell that generates patterns according to multiple transitions fault model and 2) an observation cell that monitors signal integrity violations. To fully comply with the conventional Joint Test Action Group Standard, two new instructions are used to control cells and scan activities in the integrity test mode.

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

“…Therefore, in this work, we assume that the test stimuli are loaded from an external tester to the core-test wrapper. To apply SI test at the core-level, as shown in Figure 3 [Tehranipour et al 2003], the wrapper-output cell (WOC) should be able to provide the necessary consecutive transitions to interconnects; the wrapper-input cell (WIC) needs to be equipped with a signal integrity loss sensor [Bai et al 2000;Tehranipour et al 2003] to capture the signal with noise and/or delay error.…”

“…We consider, as a starting point, that every core in the SOC uses wrapper cells as shown in Figure 3 [Tehranipour et al 2003]. These wrappers are compatible with the IEEE 1500 standard [IEEE Std.…”

“…Moreover, process variations and manufacturing defects may aggravate the SI-related problems [Natarajan et al 1998]. Since it is unacceptable to over-design the circuit to tolerate signal integrity loss in all cases and it is impossible to predict the occurrence of defects, manufacturing test strategies are essential for detecting SI-related errors [Cuviello et al 1999;Sirisaengtaksin and Gupta 2002;Tehranipour et al 2003]. …”

“…Various SI fault models [Cuviello et al 1999;Kundu et al 2005;Tehranipour et al 2004] and associated test methodologies [Bai et al 2000;Tehranipour et al 2003] have been proposed in the literature. SI-related problems are aggravated in core-based SOC designs because interconnects carrying signals between embedded cores tend to be long and hence they suffer more from parasitic effects [Nordholz et al 1998].…”

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

“…An online testing technique that captures noise-induced logic errors using a double sampling data checking is presented in [17]. In [18], the authors present an on-chip mechanism for testing SoC interconnects for SI using an enhanced JTAG architecture. Test-wrapper designs for the detection of signal-SI faults on core-external interconnect of SoCs is presented in [19].…”