Testing SoC Interconnects for Signal Integrity Using Extended JTAG Architecture

Abstract

Abstract-As technology shrinks and working frequency reaches the multigigahertz range, designing and testing interconnects are no longer trivial issues. In this paper, we propose an enhanced boundary-scan architecture to test high-speed interconnects for signal integrity. This architecture includes: 1) a modified driving cell that generates patterns according to multiple transitions fault model and 2) an observation cell that monitors signal integrity violations. To fully comply with the conventional Joint Test Action Group Standard, two new instructions are used to control cells and scan activities in the integrity test mode.

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

“…If all the physical defects are capacitive or resistive, all MA/MAL faults can be targeted using a pattern count that is linear in the number of interconnects. When inductance is considered, however, such test patterns may not be able to generate maximum noise/delay on the victim line [Chen et al 1999;Naffziger 1999]; hence, Tehranipour et al [2004] presented a multiple transition (MT) fault model that covers all transitions on victim and multiple transitions on aggressors. The number of test patterns for this MT fault model, however, is exponential in the number of interconnects under test.…”

“…For a set of N interconnects, the number of test patterns for the reduced-MT fault model is approximately N · 2 2k+2 . Built-In Self-Test (BIST) has been a popular test method used to detect SIrelated errors [Sekar and Dey 2002;Tehranipour et al 2004]. In this approach, driver side of interconnects are equipped with test generators to generate transitions on the aggressors and victims, while at the receiver side, various types of integrity-loss sensor (ILS) cells are embedded to detect SI-related errors.…”

“…We assume that the test stimuli for SI faults are given to us a priori; these stimuli can take the form of functional patterns, pseudorandom patterns, and/or patterns generated for various SI fault models [Cuviello et al 1999;Sirisaengtaksin and Gupta 2002;Tehranipour et al 2004]. Since a victim interconnect is mainly affected by its neighboring aggressors [Kundu et al 2005], the signal integrity test patterns typically feature a large number of don't-care bits.…”

“…Various SI fault models [Cuviello et al 1999;Kundu et al 2005;Tehranipour et al 2004] and associated test methodologies [Bai et al 2000;Tehranipour et al 2003] have been proposed in the literature. SI-related problems are aggravated in core-based SOC designs because interconnects carrying signals between embedded cores tend to be long and hence they suffer more from parasitic effects [Nordholz et al 1998].…”

Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs

“…The IEEE 1500 standard wrapper [11] can potentially support SI interconnect test if two-pattern at-speed signal transition capability is provided at the core test wrapper of the interconnect driving side (e.g., every wrapper output cell is equipped with two flip-flops), while at the same time integrity loss sensor (ILS) cells (e.g., [24]) are added at the wrapper of the interconnect receiving side. Unfortunately, such a design is unlikely to provide an acceptable quality level for interconnect SI test.…”