Testing Technique of BIST: A Survey

Abstract

As the compactness of system-on-chip (SoC) increase, it becomes striking to integrate dedicated test logic on a chip.

Built in Self Test Architecture Using Logic Module

“…These techniques are evaluated based on the concurrent test latency (CTL) and the hardware overhead, whereas the circuit operates normally. In this brief discussion, researcher presents input ng concurrent BIST technique [4], which is based on the technique of monitoring a set of vectors reaching the circuit inputs during normal operation, and the use of a static like structure to store the comparative locations of the vectors that attain the circuit inputs in the examined window. After analysis of so many journals and articles we conclude that, there -in Self-test (BIST) are On-Line BIST and Off-Line BIST line BIST Testing technique operating in normal operation…”

“…In the earlier period, several researchers and authors have investigated the BIST testing techniques for the detection of fault coverage [4] Proposed an Adaptive Low Power RTPG for BIST based test applications. In this research paper, researcher concerned about the power reduction during But methods to reduce shift power will results in test coverage loss.…”

“…In C-BIST [4] was the first input vector monitoring concurrent BIST technique proposed, and suffers from long hardware overhead and CTL; therefore modifications have been proposed, Order Independent Signature Analysis Technique (OISAT) [10], Multiple Hardware Sig-nature Analysis Technique (MHSAT) [9], RAM-based Concurrent BIST (RCBIST) [15], Window Monitoring Concurrent BIST (WMCBIST) [3], and Square Windows Monitoring Concurrent BIST (SWIM) [11]. The comparisons will be performed with respect to the hardware overhead.…”