Tests for address decoder delay faults in RAMs due to inter-gate opens

Goor, A.J. van de; Hamdioui, Said; Al-Ars, Zaid

doi:10.1109/etsym.2004.1347646

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Cited by 3 publications

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“…In [10], the authors try to provide the entire space of faults in the peripheral circuits of SRAM and the analysis of test conditions. In other works, SRAM address decoder delay faults [11], [12] and precharge delay faults [13] are presented by using defect injection. However, these delay fault models are all restricted to a certain part of the memory, and are all for SRAM circuits.…”

Section: Introductionmentioning

confidence: 99%

SDRAM Delay Fault Modeling and Performance Testing

Hsing

Huang

Yeh

et al. 2007

25th IEEE VLSI Test Symmposium (VTS'07)

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DRAM timing parameter testing has always been considered a time-consuming process. This paper presents a systematic approach to analysis and classification of the synchronous DRAM (SDRAM) delay failure modes. Four delay fault models with March expression are proposed to cover important DRAM timing parameters. By at-speed March testing of these four types of delay faults, we can verify the DRAM timing specifications.

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