The 68040 processor. I. Design and implementation

Edenfield, R.W.; Gallup, M.G.; Ledbetter, W B; McGarity, R.; Quintana, E.; Reininger, R.A.

doi:10.1109/40.46770

Cited by 20 publications

(2 citation statements)

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“…Hazards caused by a branch can be reduced by executing some of its operations in advance. For example, the Motorola 68040 [3] has an additional adder to compute the target address as soon as a branch is fetched. c) Brunch prediction.…”

Section: Reducing the Cost Of Branchesmentioning

confidence: 99%

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Reducing branch delay to zero in pipelined processors

González

Llaberia

1993

IEEE Trans. Comput.

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Abstract-A mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution of branches. The implementation of this mechanism using a Branch Target Instruction Memory is described. An analytical model of the performance of this implementation is presented, which allows us to measure the efficiency of the mechanism with a very low computational cost. The model is used to determine the size of cache lines that maximizes the processor performance, to compare the performance of the mechanism with other schemes, and to analyze the performance of the mechanism with two alternative cache organizations.Index Terms-Branch instructions, branch target instruction memory, computer architecture, instruction cache memory, instruction dependencies, performance evaluation, pipelined processors.

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Section: Reducing the Cost Of Branchesmentioning

confidence: 99%

“…Permutations by cutting and shuffling were studied by Golomb [3]. Computational applications of the shuffle were conceived by Batcher [l] for bitonic sorting and by Singleton [13] and Pease [9] for the fast Fourier transform.…”

Section: Introductionmentioning

confidence: 99%