The Analytical Models of Fringe Parasitic Capacitance of FinFET - A Review

Abstract

When planar MOSFET encounters its own scaling limit, FinFET was introduced and successfully replaced the traditional MOSFET. FinFET owns its privilege over the planar MOSFET for its high tolerance to short channel effect. However, due to FinFET’s 3D structure, high parasitic capacitance compared to planar MOSFET significantly degrades the transistor speed because of RC delay. This paper provides a review on the fringe capacitance of FinFET device based on the accuracy to experimental data of the two-dimensional and three-dimensional analytical models. Those models take the external and internal parasitic capacitance component into account. The three-dimensional model outperforms the two-dimensional model in levels of precision but requires more parameters and time to establish.