The Architecture and Development Flow of the S5 Software Configurable Processor

Abstract

A software configurable processor (SCP) is a hybrid device that couples a conventional processor datapath with programmable logic to allow application programs to dynamically customize the instruction set. SCP architectures can offer significant performance gains by exploiting data parallelism, operator specialization and deep pipelines. The S5000 is a family of high performance software configurable processors for embedded applications. The S5000 consists of a conventional 32-bit RISC processor coupled with a programmable Instruction Set Extension Fabric (ISEF). To develop an application for the S5 the programmer identifies critical sections to be accelerated, writes one or more extension instructions as functions in a variant of the C programming language, and accesses those functions from the application program. Performance gains of more than an order of magnitude over the unaccelerated processor can be achieved.

Exploration and Customization of FPGA-Based Soft Processors

“…Commercial customizable processors are available from Tensilica [7] for application-specific integrated circuits (ASICs), Stretch [8] as an off-the-shelf part, and others which allow designers to tune the processor with additional hardware instructions to better match their application requirements. Altera Nios [1] and Xilinx Microblaze [2] are processors meant for FPGA designs which also allow customized instructions or hardware, and are typically available in only a few microarchitectural variants.…”

Processor customization for wearable bio-monitoring platforms

“…The Stretch C compiler then fully unrolls any loop with constant iteration counts. There are three main sources of performance gain from the custom instructions in Stretch [1]: (1) Each custom instruction can read up to three 128-bit operands and produce up to two 128-bit operands. This allows a custom instruction to exploit significant data parallelism as multiple data values can be packed together in a single 128-bit operand.…”

“…In this work, we choose Stretch customizable processor [1] as the hardware platform. Figure 2 shows the Stretch S5 engine that incorporates Tensilica Xtensa RISC processor [3] and the Stretch Instruction Set Extension Fabric (ISEF).…”

A Survey on Dynamically Reconfigurable Processors

“…In such systems, a task executed in the PE array is treated as a reconfigurable operation of the host processor, and the dynamically reconfigurable processor behaves like a kind of pipelined execution unit of the host processor. Similarly, S5-engine is composed in a Tensillica's configurable processor Xtensa [11].…”