The architecture and programming of the Ametek series 2010 multicomputer

Seitz, Charles L.; Athas, W.C.; Flaig, Charles M.; Martin, Alain J.; Seizovic, Jakov N.; Steele, Craig S.; Su, W-K.

doi:10.1145/62297.62302

Cited by 130 publications

(41 citation statements)

References 5 publications

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“…In most contemporary concurrent computers, this is the dominant component of latency. Because of their low-latency, high throughput, and affinity for implementation in VLSI, these k-ary n-cube networks with n = 2 or 3 have been used successfully in the design of several concurrent computers including the Ametek 2010 [19], the J-Machine However, low-dimensional k-ary n-cube interconnection networks have two significant shortcomings:…”

mentioning

confidence: 99%

Express cubes: improving the performance of k-ary n-cube interconnection networks

Dally

1991

IEEE Trans. Comput.

182

136

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Abstruct-Express cubes are k-ary n-cube interconnection networks augmented by express channels that provide a short path for nonlocal messages. An express cube combines the logarithmic diameter of a multistage network with the wire-efficiency and ability to exploit locality of a low-dimensional mesh network. The insertion of express channels reduces the network diameter and thus the distance component of network latency. Wire length is increased allowing networks to operate with latencies that approach the physical speed-of-light limitation rather than being limited by node delays. Express channels increase wire bisection in a manner that allows the bisection to be controlled independent of the choice of radix, dimension, and channel width. By increasing wire bisection to saturate the available wiring media, throughput can be substantially increased. With an express cube both latency and throughput are wire-limited and within a small factor of the physical limit on performance. Express channels may be inserted into existing interconnection networks using interchanges. No changes to the local communication controllers are required.Index Terms-Communication networks, concurrent computing, interconnection networks, multicomputers, packet routing, packet switching, parallel processing, topology. An interconnection network is characterized by its topology, routing, and flow control [lo]. The topology of a network is the arrangement of its nodes and channels into a graph. Routing determines the path chosen by a message in this graph. Flow control deals with the allocation of channel and buffer resources to a message as it travels along this path. This paper deals only with topology. Express cubes can be applied independent of routing and flow control strategies. The performance of a network is measured in terms of its latency and its throughput. The latency of a message is the elapsed time from when the message send is initiated until the message is completely received. Network latency is the average message latency under specified conditions. Network throughput is the number of messages the network can deliver per unit time. Low-dimensional k-ary n-cube networks using wormhole routing have been shown to provide low latency and high throughput for networks that are wire-limited [4], [5], [9]. For n 3, the k-ary n-cube topology is wire-efficient in that it makes efficient use of the available bisection width. This topology maps into the three physical dimensions in a manner that allows messages to use all of the available bandwidth along their path without ever having to double back on themselves. Also, low-dimensional k-ary n-cubes concentrate bandwidth into a few wide channels so that the component of latency due to message length is reduced. In most contemporary concurrent computers, this is the dominant component of latency. Because of their low-latency, high throughput, and affinity for implementation in VLSI, these k-ary n-cube networks with n = 2 or 3 have been used However, low-dimensional k-ary n-cube intercon...

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mentioning

confidence: 99%

Express cubes: improving the performance of k-ary n-cube interconnection networks

Dally

1991

IEEE Trans. Comput.

182

136

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“…Studying the layout of some simple RISC processors [13], [21], [20], [15] leads to a base cost of f p PXS Â IH S transistor. That is, a minimal single issue 64-bit processor can be built in the area of 250K SRAM bits or with 250K logic transistors.…”

Section: Cost Modelmentioning

confidence: 99%

“…We arrive at this from a study of simple routers [17], [16], [13], [22]. Examples of routers with the number of transistors used in current implementations are shown in Table 2.…”

Section: Cost Modelmentioning

confidence: 99%

SimpleFit: a framework for analyzing design trade-offs in Raw architectures

Moritz

Yeung

Agarwal

2001

IEEE Trans. Parallel Distrib. Syst.

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AbstractÐThe semiconductor industry roadmap projects that advances in VLSI technology will permit more than one billion transistors on a chip by the year 2010. The MIT Raw microprocessor is a proposed architecture that strives to exploit these chip-level resources by implementing thousands of tiles, each comprising a processing element and a small amount of memory, coupled by a static two-dimensional interconnect. A compiler partitions fine-grain instruction-level parallelism across the tiles and statically schedules intertile communication over the interconnect. Because Raw microprocessors fully expose their internal hardware structure to the software, they can be viewed as a gigantic FPGA with coarse-grained tiles in which software orchestrates communication over static interconnections. One open challenge in Raw architectures is to determine their optimal grain size and balance. The grain size is the area of each tile and the balance is the proportion of area in each tile devoted to memory, processing, communication, and off-chip global I/O. If the total chip area is fixed, higher processing power per tile requires large tiles and hence reduces the total number of tiles on the chip. This paper presents SimpleFit, a novel analytical framework that designers can use to reason about the design space of Raw microprocessors. Our model is also generalizable to multiprocessors on a chip. Based on an architectural model, an application model, and a VLSI cost analysis, the framework computes the performance of applications and uses an optimization process to identify designs that will execute these applications most cost-effectively. Although the optimal machine configurations obtained vary for different applications, problem sizes, and budgets, the general trends for various applications are similar. Accordingly, for the applications studied, assuming a onr billion logic transistor equivalent area, we recommend building a Raw chip with approximately 1,000 tiles, 30 words/cycle global I/O, 20 Kbytes of local memory per tile, three to four words/cycle local communication bandwidth, and single-issue processors. This configuration will give performance near the global optimum for most applications.

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“…Parallel machines that use 2D meshes include the MIT J-Machine [7], the Symult 2010 [22], and the Intel Touchstone [19]. For simplicity, we consider square meshes and tori.…”

Section: Introductionmentioning

confidence: 99%

Fast gossiping in square meshes/tori with bounded-size packets

Lau

Zhang

2002

IEEE Trans. Parallel Distrib. Syst.

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AbstractÐGossiping is the communication problem in which each node has a unique message (token) to be transmitted to every other node. The nodes exchange their tokens by packets. A solution to the problem is judged by how many rounds of packet sending it requires. In this paper, we consider the version of the problem in which small-size packets (each carrying exactly one token) are used, the links (edges) of the network are half-duplex (only one packet can flow through a link at a time), and the nodes are all-port (a node's incident edges can all be active at the same time). This is also known as the H* model. We study the 2D square mesh and the 2D square torus. An improved, asymptotically optimal algorithm for the mesh and an optimal algorithm for the torus are presented.

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The architecture and programming of the Ametek series 2010 multicomputer

Cited by 130 publications

References 5 publications

Express cubes: improving the performance of k-ary n-cube interconnection networks

Express cubes: improving the performance of k-ary n-cube interconnection networks

SimpleFit: a framework for analyzing design trade-offs in Raw architectures

Fast gossiping in square meshes/tori with bounded-size packets

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