The ARPA-MT Embedded SMT Processor and Its RTOS Hardware Accelerator

Oliveira, Arnaldo S. R.; Almeida, Luciana Faletti; Ferrari, António B.

doi:10.1109/tie.2009.2028359

Cited by 40 publications

(24 citation statements)

References 27 publications

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“…ARPA-MT system proposed by A. S. R. Oliveira et al in [43] presents multi threading processor with five stage pipeline. It supports heterogeneous task and context switches without hampering the processor performance.…”

Section: Z Murtaza S Khan Et Al Describe Srtos Inmentioning

confidence: 99%

Untitled

2015

IJESA

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Section: Z Murtaza S Khan Et Al Describe Srtos Inmentioning

confidence: 99%

Untitled

2015

IJESA

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“…Oliveira et al [6] proposed a customizable multi-threading processor architecture, which hardwires some features of a RTOS, increasing determinism, which supports the processor's use in real-time applications.…”

Section: IImentioning

confidence: 99%

“…Aggressive branch prediction mechanisms are employed to increase throughput [1] and to decrease power consumption [2]; memory hierarchies (Level 1 and Level 2 caches) are used to mask the speed gap between memories and processors [3]; super-pipelined and Simultaneous MultiThreading (SMT) processors offer significantly higher throughput than previous architectures [4]; and in the embedded world, the advent of FPGAs and softcore processors led the way to hardware implementations of traditional software features, such as commonly used functions in an application [5] or even RTOSs' features [6]. All these optimizations work on one of two levels: either at the machine level (e.g., cache performance is invisible to the programmer, although not to the compiler) or at the application/middleware level (e.g., custom hardware accelerators).…”

Section: Introductionmentioning

confidence: 99%

Processor's micro-architectural support for runtime environment

Garcia

Gomes

Salgado

et al. 2011

2011 9th IEEE International Conference on Industrial Informatics

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This paper presents a micro-architectural feature in a processor's datapath to support the C language's runtime environment. A hardware accelerator for C function calls was embedded in a processor core and its impact on area and performance was evaluated. Results show that the accelerator offers a performance improvement in several different processor configurations. The performance gain depends on the utilized processor configuration, especially on memory access contention.

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“…Real-time system is designed as a solution to fulfil the special needs of these real-time requirements. To solve this, efforts have been made in fields such as real-time buses, real-time microprocessors [11], real-time operating systems [12], realtime application software and cache scheduling [5,17].…”

Section: Introductionmentioning

confidence: 99%

Hard real-time bus architecture and arbitration algorithm based on AMBA

Ding

2015

2015 International Conference on Information and Communications Technologies (ICT 2015)

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Real-time processors are growly used in embedded applications. Considering that the time cost in data transfer among devices is much more than the time used for computation and operation, it's important to design a high-speed real-time bus structure in real-time systems. This paper offers a deep investigation to the characteristics of real-time systems as well as the basic structure of real-time processors and real-time buses. We designed a high-speed and time-predictable bus architecture called RTBus, where high-performance AXI protocol is employed. To accurately calculate the bus access time for master devices, a two-level real-time bus arbitration algorithm, which adopts the warning-line judgment mechanism and simulated annealing algorithm, is proposed for the operation of the RTBus. Finally, it is proved that RTBus provides a good solution to the conflicts when sharing resources in real-time processors.

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The ARPA-MT Embedded SMT Processor and Its RTOS Hardware Accelerator

Cited by 40 publications

References 27 publications

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Processor's micro-architectural support for runtime environment

Hard real-time bus architecture and arbitration algorithm based on AMBA

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