The Associative Memory Serial Link Processor for the Fast TracKer (FTK) at ATLAS

Andreani, A.; Annovi, A.; Beccherle, R.; Beretta, M.; Biesuz, N. V.; Billereau, W.; Cipriani, R.; Citraro, Saverio; Citterio, M.; Colombo, Alessandro; Combe, J. M.; Crescioli, F.; Dimas, D.; Donati, S.; Gentsos, C.; Giannetti, P.; Kordas, K.; Lanza, A.; Liberali, V.; Luciano, P.; Magalotti, D.; Neroutsos, P.; Nikolaidis, S.; Piendibene, M.; Rossi, Enrico; Sakellariou, A.; Shojaii, J.; Sotiropoulou, C. L.; Stabile, A.; Vulliez, P.

doi:10.1088/1748-0221/9/11/c11006

Cited by 9 publications

(6 citation statements)

References 9 publications

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“…The processors are designed to cope with the pattern recognition task [11] using the new version of the AM device. The track parameters are then measured for each pattern using a precision track fit [7] performed with the latest generation of FPGA devices.…”

Section: Demonstrator System Overviewmentioning

confidence: 99%

L1 track trigger for the CMS HL-LHC upgrade using AM chips and FPGAs

Fedi

2017

EPJ Web Conf.

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Abstract.The increase of luminosity at the HL-LHC will require the introduction of tracker information in CMS's Level-1 trigger system to maintain an acceptable trigger rate when selecting interesting events, despite the order of magnitude increase in minimum bias interactions. To meet the latency requirements, dedicated hardware has to be used. This paper presents the results of tests of a prototype system (pattern recognition mezzanine) as core of pattern recognition and track fitting for the CMS experiment, combining the power of both associative memory custom ASICs and modern Field Programmable Gate Array (FPGA) devices. The mezzanine uses the latest available associative memory devices (AM06) and the most modern Xilinx Ultrascale FPGAs. The results of the test for a complete tower comprising about 0.5 million patterns is presented, using as simulated input events traversing the upgraded CMS detector. The paper shows the performance of the pattern matching, track finding and track fitting, along with the latency and processing time needed. The p T resolution over p T of the muons measured using the reconstruction algorithm is at the order of 1% in the range 3-100 GeV/c.

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Section: Demonstrator System Overviewmentioning

confidence: 99%

L1 track trigger for the CMS HL-LHC upgrade using AM chips and FPGAs

Fedi

2017

EPJ Web Conf.

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“…Smaller prototypes were designed to demostrate the chip functionality and performance at the 65 nm node: the AM04 [6], and the two versions of the AM05 [7].…”

Section: The Associative Memory Chipmentioning

confidence: 99%

An Associative Memory Chip for the Trigger System of the ATLAS Experiment

Shojaii¹

2017

Proceedings of the 25th International Workshop on Vertex Detectors — PoS(Vertex 2016)

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The AM06 is the 6 th version of a large associative memory chip designed in 65 nm CMOS technology. The AM06 operates as a highly parallel ASIC processor for pattern recognition in the ATLAS experiment at CERN. It is the core of the Fast TracKer electronic system, which is tailored for on-line track finding in the trigger system of the ATLAS experiment. The Fast TracKer system is able to process events up to 100 kHz in real time. The AM06 is a complex chip, and it has been designed combining full-custom memory arrays, standard logic cells and IP blocks. It contains memory banks that store data organized in 18 bit words; a group of 8 words is called a pattern. It accepts as input 16-bit words at a rate of 100 MHz, which are serialized with an 8b/10b encoding, thus giving a serial data rate equal to 2 Gbit/s. The chip silicon area is 168 mm 2 ; it contains 421 millions of transistors and it stores 2 17 patterns. Moreover, the associative memory is suitable also for other interdisciplinary applications (i.e., general purpose image filtering and analysis). In the near future we plan to design a more powerful and flexible chip in 28 nm CMOS technology.

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“…Each Pulsar board hosts 4 FMC mezzanines equipped with AM chips and an FPGA performing the pattern recognition and track fitting of a given particular event. Depending upon the There are currently two different types of mezzanine boards under development: a first one developed by INFN is a 14.9 × 14.9 cm 2 card hosting two FMC connectors designed to satisfy the VITA 57.1 standard specification, a Kintex 7 FPGA (XC7K355T) and 16 AM chips, which have been produced for the ATLAS FTK [9,10]. The board has been first developed to host AM05 chips, to test the basic functionality of the serial links, even if the number of patterns stored in each chip will be modest (2,048).…”

Section: Associative Memory (Am) Plus Fpga Based Approachmentioning

confidence: 99%

Track Finding in CMS for the Level-1 Trigger at the HL-LHC

2016

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The High Luminosity LHC (HL-LHC) will deliver luminosities of up to 5 × 10 34 Hz/cm 2 , with an average of about 140 overlapping proton-proton collisions per bunch crossing. These extreme pileup conditions place stringent requirements on the trigger system to be able to cope with the resulting event rates. A key component of the CMS upgrade for HL-LHC is a track trigger system which would identify tracks with transverse momentum above 2 GeV/c already at the first-level trigger. This paper presents the status of proposals for implementing the L1 tracking in conjunction with the planned upgrade for the silicon tracker of the CMS experiment. ABSTRACT: The High Luminosity LHC (HL-LHC) will deliver luminosities of up to 5 × 10 34 Hz/cm 2 , with an average of about 140 overlapping proton-proton collisions per bunch crossing. These extreme pileup conditions place stringent requirements on the trigger system to be able to cope with the resulting event rates. A key component of the CMS upgrade for HL-LHC is a track trigger system which would identify tracks with transverse momentum above 2 GeV/c already at the first-level trigger. This paper presents the status of proposals for implementing the L1 tracking in conjunction with the planned upgrade for the silicon tracker of the CMS experiment.

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The Associative Memory Serial Link Processor for the Fast TracKer (FTK) at ATLAS

Cited by 9 publications

References 9 publications

L1 track trigger for the CMS HL-LHC upgrade using AM chips and FPGAs

L1 track trigger for the CMS HL-LHC upgrade using AM chips and FPGAs

An Associative Memory Chip for the Trigger System of the ATLAS Experiment

Track Finding in CMS for the Level-1 Trigger at the HL-LHC

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