The Ballast methodology for structured partial scan design

Gupta, Rajesh K.; Breuer, M.A.

doi:10.1109/12.54846

Cited by 163 publications

(59 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Gupta et al [11], [13] defined a subclass of acyclic sequential circuits called "balanced" that avoided the test generation for multiple faults. FFs via a partial scan.…”

Section: Circuit Subclasses and Atpg Methodsmentioning

confidence: 99%

“…Using the idea that the circuit should be balanced [13] for combinational ATPG to be effective, we create a balanced ATPG model (BAM) for any given acyclic circuit. All unbalanced fanouts, i.e., fanouts reconverging with different sequential depths, are moved toward primary inputs using a retiming-like transformation.…”

Section: New Combinational Atpg Methodsmentioning

confidence: 99%

“…Inoue et al [18], [19] give a constructive definition Manuscript The focus of our paper is efficient derivation of tests for general acyclic sequential circuits using any conventional single-fault combinational ATPG program. Starting with the ideas of Miczo [26] and Gupta et al [11], [13], we develop a combinational model suitable for combinational test generation. We can then detect all testable faults and identify all untestable faults [22]- [24] for acyclic sequential circuits using combinational ATPG.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Combinational automatic test pattern generation for acyclic sequential circuits

Kim

Agrawal

Saluja

2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Abstract-It is known that the complexity of automatic test pattern generation (ATPG) for acyclic sequential circuits is similar to that of combinational ATPG. The general problem, however, requires time-frame expansion and multiple-fault detection and hence does not allow the use of available combinational ATPG programs. The first contribution of this work is a combinational single-fault ATPG method for the most general class of acyclic sequential circuits. Without inserting any real hardware, we create a functionally equivalent "balanced" ATPG model of the circuit in which all reconverging paths have the same sequential depth. Some primary inputs and gates are duplicated in this model, which is converted into a combinational circuit by shorting all flip-flops. A test vector obtained by a combinational ATPG program for a fault in this combinational circuit is transformed into a test sequence to detect a corresponding fault in the original sequential circuit. A combinational ATPG program finds tests for all but a small set of faults that must be explicitly detected as multiple-faults. Those are modeled for ATPG using the second contribution of this work, which is a generalized method to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most + 3 modeling gates for a fault of multiplicity . We show that the modeled circuit is functionally equivalent to the original circuit and the targeted multiple fault is equivalent to the modeled single stuck-at fault. Benchmark results show at least an order of magnitude saving in the ATPG CPU time by the new combinational method over sequential ATPG.Index Terms-Acyclic sequential circuit, automatic test pattern generation (ATPG), balanced model, combinational test generation, design for test (DFT), partial scan, test.

show abstract

“…Gupta et al [11], [13] defined a subclass of acyclic sequential circuits called "balanced" that avoided the test generation for multiple faults. FFs via a partial scan.…”

Section: Circuit Subclasses and Atpg Methodsmentioning

confidence: 99%

Section: New Combinational Atpg Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Combinational automatic test pattern generation for acyclic sequential circuits

Kim

Agrawal

Saluja

2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…Partial-scan mthods can be categorized as: structure based [7][8][9][10][11], testability-measure based [12], and test-generation based [13] methods. Of the three, structure based methods have been most successful.…”

Section: Introductionmentioning

confidence: 99%

SPARTAN: a spectral and information theoretic approach to partial-scan

Khan

Bushnell

Devanathan

et al. 2007

2007 IEEE International Test Conference

View full text Add to dashboard Cite

show abstract

“…This partial scan design method selects FFs to replace with scan FFs so that circuit structure has acyclic structure [8][9][10][11] in order to guarantee high fault efficiency. Moreover, the fault in an acyclic sequential circuit has the feature [2] that it is detectable with the number of ATPG patterns which is not more than sequential depth [2,6]+1 of the circuit.…”

Section: (2) the Basic Concept Of The Partial Scan Design Methodsmentioning

confidence: 99%

Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times

Hosokawa¹,

Yoshimura²,

Ohta³

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

View full text Add to dashboard Cite

As an LSI is on the two-dimensional plane, the number of external pins of an LSI does not equally increase to the number of gates. Therefore, the number of flip-flops on a scan path is relatively increasing. As the results, the test application time becomes longer. In this paper, three new DFT strategies are proposed to reduce the test application time. Experimental results showed the DFT strategies reduced the test application times by 46 to 82% compared with a conventional full scan design method. INTRODUCTIONAccording to the recent advance of semiconductor process technology, the circuit densities on LSI are growing and the automatic test design becomes more important. Because the automatic test pattern generation (ATPG) for a sequential circuit is difficult in general, a design for testability (DFT) must be applied to obtain high fault efficiency. The full scan design method [1,2] is one of popular DFT methods, so far. In the full scan design method, all flip-flops (FFs) are replaced with scan FFs. A scan FF is equivalent to a primary input and a primary output at the test mode. In the scan design method, ATPG can be performed for the portion of the circuit excluding the scan path, which is the kernel circuit. Since the kernel circuit of the full scan design LSI is a combinational one, a combinational ATPG algorithm can be applied to it and it can obtain high fault efficiency.Test application time by the scan design method is the product of the test length of an automatic test equipment (ATE) of the formula (1) and the clock period of the ATE. TL = (TP +1) × MSL + TP …(1)In the formula(1), TL is test length of an ATE, TP is the number of test patterns of the kernel circuit and is called the ATPG patterns, MSL is the maximum number of scan FFs on one scan paths and is called the maximum scan path length.As the increasing number of the external pins on LSI boundary is slower than the increase of the size of an LSI, the number of scan FFs on a scan path connected to the external pins increases relatively. Consequently, the full-scan-design test application time becomes longer. The formula (1) shows that the test length of a scan design method can be shortened by shortening the maximum scan path length and/or by reducing the number of ATPG patterns.In this paper, three DFT strategies are proposed in order to reduce test application times as follows:(1) DFT strategy1: applies the full scan design method with test point insertions to an LSI. (2) DFT strategy2: applies the partial scan design method to an LSI. (3) DFT strategy3: applies the partial scan design method with test point insertions to an LSI. The next section explains the motivation of this research. In section 3, the three DFT strategies are proposed. The effectiveness of the strategies by applying them to practical LSIs are showed in section 4. The conclusion and our future works are described in section 5. MOTIVATIONThe road map of ITRS [3] predicts that the number of gates increases at a rate of about 40% per year, and the number of externa...

show abstract

The Ballast methodology for structured partial scan design

Cited by 163 publications

References 5 publications

Combinational automatic test pattern generation for acyclic sequential circuits

Combinational automatic test pattern generation for acyclic sequential circuits

SPARTAN: a spectral and information theoretic approach to partial-scan

Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times

Contact Info

Product

Resources

About