The best of both: High-performance and deterministic real-time executive by application-specific multi-core SoCs

Vaas, Steffen; Ulbrich, Peter; Reichenbach, Marc; Fey, Dietmar

doi:10.1109/dasip.2017.8122107

Cited by 6 publications

(2 citation statements)

References 12 publications

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“…For example, ARM11 branch instructions require three clock cycles if taken, but one cycle if not taken [11]. In PowerPC 755, a simple addition may take anywhere from 3 up to 321 cycles [12] due to its non-compositional architecture [13] that produces a domino effect.…”

Section: Introductionmentioning

confidence: 99%

A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture

Ali

Pora

2022

Electronics

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This paper proposes a new deterministic branch prediction unit to achieve a uniformly timed instruction set architecture (ISA). The deterministic ISA is achieved by utilizing two address buses in conjunction with dual-port block RAMs that are common in commercial FPGAs. The goal is to remove mandatory branch and load delays to achieve a uniform one clock cycle per every instruction. To demonstrate the concept, the proposed architecture is applied to the Xilinx PicoBlaze firm core. The result is a new soft core named DAP-Zipi8 that reduces the clock per instruction (CPI) metric of PicoBlaze from two to one at the expense of extra logic and a longer critical path. The increased critical path reduces maximum achievable clock speed from 357.509 MHz to 224.022 MHz. Merging the gain in CPI with the loss in maximum clock frequency still improves overall processor performance by 18.28–19.49%. The high-performance deterministic DAP-Zipi8 is a viable choice for hard RTES applications.

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Section: Introductionmentioning

confidence: 99%

A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture

Ali

Pora

2022

Electronics

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“…For example, most branch instructions require more clock cycles if taken than if not. The ARM11 needs one clock cycle for untaken, but three clock cycles for taken branches [239] In PowerPC 755 a simple addition may take between 3 to 321 cycles [240] due to its non-compositional architecture [241] that produces domino effect.…”

Section: Resultsmentioning

confidence: 99%

A morphable FPGA soft processor using LLVM infrastructure targeting low-power application-specific embedded systems

Ali¹

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The reconfigurable computing (RC) aims to combine the flexibility of General-Purpose Processor (GPP) with performance of Application Specific Integrated Circuits (ASIC). There are several architectures proposed since RC’s inception in 1960s, but all have failed to become mainstream. The main factor preventing RC to become common practice is its requirement for implementers of algorithms (programmers) to be familiar with hardware design. In RC, a hardened processor cooperates with a dynamic reconfigurable Hardware Accelerator (HA) which is implemented on Field-Programmable Gate Array (FPGA). The HA implements crucial software kernel on hardware to increase performance and its design demands digital circuit expertise. In this paper a novel RC architecture is proposed that keeps the decades old programming practices intact while harnessing the power of HA. The architecture uses LLVM compiler infrastructure to receive an algorithm and then outputs the equivalent machine language, it then finds the most frequent instruction pairs and generates equivalent RC circuit called “Miniature Accelerator (MA)”. The instruction pairs are dynamically removed from pipeline and MA computed result replaces them in parallel. To demonstrate the concept the Fast Fourier Transform (FFT) algorithm which is core Digital signal processing (DSP) kernel is written in C and then executed on an ARM Cortex-M0. The execution of FFT function is improved by 14.12%. The proposed adaptive processor is fully backward compatible, compilation is automated, and no modification of exiting software or established programming paradigms is required.

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Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands

Vaas

Ulbrich

Reichenbach

et al. 2018

J Sign Process Syst

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The best of both: High-performance and deterministic real-time executive by application-specific multi-core SoCs

Cited by 6 publications

References 12 publications

A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture

A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture

A morphable FPGA soft processor using LLVM infrastructure targeting low-power application-specific embedded systems

Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands

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