The Challenges of Massive On-Chip Concurrency

Bousias, K.; Jesshope, Chris

doi:10.1007/11572961_14

Cited by 6 publications

(1 citation statement)

References 20 publications

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“…S-Net program is compiled down to pthreadedC (uTC ) [3] which is used as user programming language. ,uTC is a rather profound but simple extension to the C language, allowing it to capture massive thread-based concurrency.…”

Section: Inputsmentioning

confidence: 99%

ÆTHER: Dynamic and Self adaptive Middleware

Farhan

Muller

Auguin

2007

2007 IEEE International Multitopic Conference

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The development of reconfigurable devices that could make themselves domain-specialized at run time is becoming more and more common. Future reconfigurable architecture will have these computing devices as basic blocks, and reconfigurable architecture could make assemblies of these devices, on the fly, to execute concurrent applications. The migration from completely generic lookup tables and highly connected routing fabrics to self adaptive specialized coarse-grain reconfigurable devices and very structured communication resources presents designers with the problem of how to best customize the system based upon anticipated usage. Then there is a need of not only exploiting parallelism from applications at micro-thread level, dynamically, but system also starves for a dynamic and self adaptive middleware to schedule these micro-threads on thousands of such computing devices. This paper focuses at the problem of dynamic allocation and scheduling of resources to numbers of applications on such architecture.

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Section: Inputsmentioning

confidence: 99%

ÆTHER: Dynamic and Self adaptive Middleware

Farhan

Muller

Auguin

2007

2007 IEEE International Multitopic Conference

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μTC – An Intermediate Language for Programming Chip Multiprocessors

Jesshope

2006

Advances in Computer Systems Architecture

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Supporting Microthread Scheduling and Synchronisation in CMPs

Bell

Hasasneh

Jesshope

2006

Int J Parallel Prog

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Chip multiprocessors (CMPs) hold great promise for achieving scalability in future systems. Microthreaded CMPs add a means of exploiting legacy code in such systems. Using this model, compilers generate parametric concurrency from sequential source code, which can be used to optimise a range of operational parameters such as power and performance over many orders of magnitude, given a scalable implementation. This paper shows scalability in performance, power and most importantly, in silicon implementation, the main contribution of this paper. The microthread model requires dynamic register allocation and a hardware scheduler, which must support hundreds of microthreads per processor. The scheduler must support thread creation, context switching and thread rescheduling on every machine cycle to fully support this model, which is a significant challenge. Scalable implementations of such support structures are given and the feasibility of large-scale CMPs is investigated by giving detailed area estimate of these structures.

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The Challenges of Massive On-Chip Concurrency

Cited by 6 publications

References 20 publications

ÆTHER: Dynamic and Self adaptive Middleware

ÆTHER: Dynamic and Self adaptive Middleware

μTC – An Intermediate Language for Programming Chip Multiprocessors

Supporting Microthread Scheduling and Synchronisation in CMPs

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