The Characteristics and Control of Body-to-Body Leakage Current in PD-SOI

Abstract

Body-to-body leakage ͑BBL͒ current in a partially depleted silicon-on-insulator ͑PD-SOI͒ device is increased significantly as polyspacing ͑PS͒ is reduced in technology scaling. We found out that the BBL has a great impact to Vt variation. We have demonstrated that the BBL can be minimized drastically by implant optimization. The dependence of the BBL on silicon film thickness, e-SiGe structure, and dopant diffusivity is also discussed in this paper. The layout effect of the BBL current in PD-SOI devices has been characterized with different PSs, device widths, and polylengths. Finally, we have demonstrated that the BBL current can be reduced below junction leakage level.Silicon-on-insulator ͑SOI͒ complementary metal oxide semiconductor ͑CMOS͒ has been widely used recently due to its better device performance and scalability. Partially depleted silicon-oninsulator ͑PD-SOI͒ has a similar device structure to a bulk device. As a consequence, the PD-SOI can be fabricated in a standard bulk CMOS process. SOI devices have better circuit performance and lower power consumption due to lower channel doping and smaller parasitic capacitances. However, PD-SOI devices possess several unique behaviors that do not exist in bulk devices such as kink effect, 1-3 self-heating effect, 4-6 history delay effect, 7,8 and pass-gate leakage. 9,10 Those effects have been actively studied and modeled. For the two stack PD-SOI devices sharing a common diffusion area, the bodies of the two devices are isolated by a common source/drain ͑S/D͒ junction. If the common S/D junction does not abut the buried oxide ͑BOX͒, a leakage path is formed between the two bodies. The body-to-body leakage ͑BBL͒ induces body potential change and Vt shift, as reported in Refs. 11 and 12. Besides, ac performance is degraded because of the increase in the S/D junction capacitance. In an advanced SOI technology, aggressive scaling of the junction depth leads to a significant increase in the BBL current. The BBL can have the following adverse effects on circuit operation: ͑i͒ Higher junction capacitance due to the larger junction area, ͑ii͒ Vt shift due to the change in body potential, and ͑iii͒ failure of circuit function if device Vt is significantly changed. As a result, the BBL effect must be taken into consideration when optimizing the S/D junction profile in PD-SOI devices.The accuracy of device modeling becomes increasingly important in modern circuit design. Although several attempts have been made on the modeling and simulation of the BBL, very few experimental results have been reported. The BBL effect also depends on the device geometries such as polygate spacing. The geometry effect must also be taken into consideration when optimizing the S/D junction profile.This paper presents the experimental and simulation results of the BBL effect and its dependences on back-gate bias, polygate spacing, device width, silicon layer thickness, and S/D implant conditions. The impact of the Vb shift to circuit function caused by the BBL in stack PD-SOI devices has bee...