Abstract. An extensive on-wafer experimental campaign is performed to extract the thermal resistance of state-of-the-art toward-THz silicon germanium bipolar transistors designed and developed within the European DOTFIVE project. The dependence of this critical parameter on scaling, as well as on the emitter layout, is carefully evaluated, and the resulting junction temperatures are determined.
IntroductionSilicon germanium (SiGe) bipolar technology is increasingly adopted in a large variety of mm-wave and near-THz applications, like high-bandwidth communications, optical transmission, medical equipments, and automotive radars. An important contribution to this trend in the European scenario has been provided by the recently-ended DOTFIVE project [1] aimed at demonstrating heterojunction bipolar transistors (HBTs) with maximum oscillation frequency f max =0.5 THz [2]-[4], which the newborn DOTSEVEN [5] is expected to boost to 0.7 THz. The need for improving the performance of SiGe transistors has motivated a constant technological effort to allow aggressive lateral and vertical scaling. However, this is leading to unsustainable thermal issues induced by (i) the increase in current (and power) density, as clearly stated in a comprehensive review paper [6], and (ii) the reduction of the spacing between the intrinsic region and shallow/deep trenches filled with low thermal conductivity materials [7], for which the thermal resistances of single-finger transistors have been pushed into the thousands of K/W [8], [9]. This paper contributes to deepen the understanding of the scaling impact on the self-heating (SH) in SiGe:C HBTs by means of simple DC measurements carried out on state-of-the-art devices realized in the DOTFIVE framework.