The control algorithm and the FPGA controller for non-interruptive rearrangeable Log2(N, 0, p) switching networks

Abstract

This paper presents the control algorithm for noninterruptive rearrangements in log2(N, 0, p) switching networks. The proposed algorithm is able to find a plane for any new connection in the rearrangeable switching network with no more than three rearrangements. Moreover, these rearrangements can be realized in the switching network without interrupting transmission for existing connections. Rearrangements are done by setting up a new connecting path before the old connecting path for the rearranged connection is disconnected. We also describe the FPGA implementation of this algorithm for the log2(32, 0, 4) switching network. This FPGA controller has been tested and verified.

Proposal of a New Structure for Netfpga Cards

“…NetFPGA cards, especially the ones with VirtexV, may also be used for more general purposes (not only for networking). In the FPGA chip, algorithms may be implemented, which seems to be very complicated [9][10][11][12][13], but their hardware realization (due to parallelization of some operations) may be very efficient [14][15][16].…”

Multiservice Switching Networks with Overflow Links and Resource Reservation

“…There are ways known in traffic engineering to efficiently counteract an increase in the internal blocking probability in multiservice switching networks. These methods include, for example, the application of appropriate control algorithms and the so-called repackaging and rearranging algorithms [3,10,11]. These algorithms do not impose any alterations to the structure of the switching network but are characterized by high computational complexity and, ultimately, their implementation may lead to a considerable increase in the load of control devices and significant delays in the process of setting up connections [12].…”

Packet dispatching using module matching in the modified MSM Clos-network switch

“…The main component of the central arbiter is the buffers load matrix. The implementation of this matrix in an FPGA chip is similar to the implementation of matrices for the controller of log 2 (N , 0, p) networks described in [20]. The requests sent by IMs are reordered according to the priority status and round-robin selection, and then they are processed by a combinational function implemented on logic gates in an FPGA chip.…”