The Cost of Adaptivity and Virtual Lanes in aWormhole Router

Abstract

We examine the cost in router complexity of adaptivity and virtual lanes in wormhole routers, using f-flat adaptive routers (based on a generalization of planar-adaptive routing) which include routers with a range of routing freedom. Our studies show that adaptivity is expensive because it requires additional virtual channels and much larger crossbar switches for both adaptivity and deadlock prevention. Increases of 50 to 100% in channel utilization are required to justify additional degrees of routing freedom.Three internal router architectures for virtual lanes are examined and the fully expanded crossbar is found to be most effective because it gives simplest control and minimal internal blocking. Examining router designs with from 1–16 virtual lanes indicates that 30% improvements in channel utilization are required to justify each additional virtual lane. These studies combined with published simulation results indicate that only modest numbers of virtual lanes are likely to be cost effective.

The Design and Performance Evaluation of the DI-Multicomputer

“…Dynamic interconnection demands routers with three characteristics: First, they must exhibit extremely low latency. Our implementation studies and others [4,8,17,33] show that router latencies in the 5-10 ns range are feasible if chip crossing costs are reduced with advanced packaging. Second, they must have multiple input and output ports, supplying or absorbing several packets at a time.…”

“…A DI-multicomputer node consists of three elements: a processor, memory units, and routers. However, rather than connecting the elements via a shared node bus, each element is embedded in a low-latency packet routing network, requiring a small router 4 per element. In addition to message passing, all local memory operations such as interface enables efficient use of the pin bandwidth with a simple hardware.…”

“…The performance numbers assumed for the calculation are shown in Table III and are derived from our hardware design studies [4] including SPICE simulations of multitap bus lines. We further assume that the DI-microprocessor reloads its cache lines from its four nearest neighbors, minimizing the routing delay.…”

“…The higher network clock rate for the DImicroprocessor memory interface is due to the electrical advantages of point-to-point interconnects over multitap bus lines [31,18]. Router delay is based on a number of published implementation studies [17,32] and our own designs [4,8]. The actions required to complete a cache line reload in each system are illustrated in Fig.…”

New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Virtual-Channelless Networks-on-Chip

“…VCs can increase delay in router's critical path due to extra arbitrations, thus it potentially affects the cycle time or pipeline depth of the router [20]. The same result is presented in [18], in which additional arbitration and multiplexing circuits for VCs on physical channels introduce delay into the critical path in implementing alternate routing algorithms.…”