2008
DOI: 10.1109/tpel.2007.909182
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The Current Sharing Optimization of Paralleled IGBTs in a Power Module Tile Using a PSpice Frequency Dependent Impedance Model

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Cited by 34 publications
(13 citation statements)
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“…Requirement for current sharing was determined to be within 15%, not a very strict requirement. Due to the complexities of digital control and utilized digital feedback loop compensation, previously published current sharing schemes [2,4,6,7] were not deemed practical, due to the implications on project timing and risk assessment. Based on the previous work with interleaved topologies [5,8] it was decided that a simpler approach is analyzed -a possibility of driving both inverters with identical drive signals and adding series inductors in line with the two paralleled inverters.…”
Section: Requirementsmentioning
confidence: 99%
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“…Requirement for current sharing was determined to be within 15%, not a very strict requirement. Due to the complexities of digital control and utilized digital feedback loop compensation, previously published current sharing schemes [2,4,6,7] were not deemed practical, due to the implications on project timing and risk assessment. Based on the previous work with interleaved topologies [5,8] it was decided that a simpler approach is analyzed -a possibility of driving both inverters with identical drive signals and adding series inductors in line with the two paralleled inverters.…”
Section: Requirementsmentioning
confidence: 99%
“…Major project constraints were identified as (1) fast, low risk development, (2) accurate prediction of final costs and (3) predetermined form factor (unchanged footprint, twice the height of the old system).…”
Section: Introductionmentioning
confidence: 99%
“…Thus, the collector-emitter voltage in the saturation V CE(sat) is an increasing function of T j according to Eq. (4)- (5).…”
Section: A Static Characteristic Parametersmentioning
confidence: 99%
“…In this regard, activities that deal with this issue are focused on two different areas. One area deals with issues related to the combination of multiple IGBT chips (or IGBT dies) in parallel inside an IGBT module and their sharing of the same substrate [4]- [7]. The second area of activity focuses on issues related to the parallel interconnection of IGBTs integrated in different substrates, as in the case of the interconnections of IGBT modules [8], [9] and discrete IGBTs [10].…”
Section: Introductionmentioning
confidence: 99%