The D30V/MPEG multimedia processor

Takata, Hitoshi; Watanabe, Takahiro; Nakajima, T.; Takagaki, T.; Sato, H.; Mohri, A.; Yamada, Akira; Kanamoto, Toshiki; Matsuda, Yuki; Iwade, S.; Horiba, Y.

doi:10.1109/40.782566

Cited by 11 publications

(9 citation statements)

References 6 publications

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“…The single-chip video audio signal processor (VASP) discussed by [37] consists of a video signal processing block The video signal processing block contains a DCT/Q unit and two ME units designed to implement hardwired solution of pixel I/O, full pixel motion estimation, half-pixel motion estimation, discrete cosine transform, and quantization. The D30V/MPEG [14] multimedia processor which supports real time MPEG-2 decoding has a two-way SIMD multimedia core.…”

Section: A Simd-based Architecturesmentioning

confidence: 99%

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A survey of media processing approaches

Dasu

Panchanathan

2002

IEEE Trans. Circuits Syst. Video Technol.

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Multimedia processing is becoming increasingly important with a wide variety of applications ranging from multimedia cell phones to high-definition interactive television. Media processing involves the capture, storage, manipulation and transmission of multimedia objects such as text, handwritten data, audio objects, still images, 2-D/3-D graphics, animation, and full-motion video. A number of implementation strategies have been proposed for processing multimedia data. These approaches can be broadly classified based on the evolution of processing architectures and the functionality of the processors. In order to provide media processing solutions to different consumer markets, designers have combined some of the classical features from both the functional and evolution-based classifications resulting in many hybrid solutions. We propose a categorization of existing microprocessors based on a combination of both architectural and functional flavors with examples of each approach from the latest multimedia processing families. The varying processing requirements in multimedia computing for reconfigurable multimedia processing.

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Section: A Simd-based Architecturesmentioning

confidence: 99%

“…The D30V/MPEG multimedia processor [14] also has a two-way VLIW instruction issue. The TANGRAM VLSI co-processor [19] intended as a building block for use in system-on-chip (SOC) designs for the versatile MPEG-4 multimedia standard is yet another example.…”

Section: B Vliw Processorsmentioning

confidence: 99%

A survey of media processing approaches

Dasu

Panchanathan

2002

IEEE Trans. Circuits Syst. Video Technol.

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“…The D30V [6] uses a basic dual-issue RISC architecture with instruction coded as VLIW for multimedia signal processing. Heterogeneous multiprocessor is used when there are parts of the embedded software that would need the power of digital signal processor and other parts need a micro-controller for the housekeeping activity, such as OMAP [7], VIPER [8], and HIBRID-SOC [9].…”

Section: Introductionmentioning

confidence: 99%

System-on-chip architecture with media DSP and RISC core for media application

Liu

2006

SPIE Proceedings

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Systems-on-chips provide single-chip solutions in many embedded applications to meet the applications size and power requirements. Media processing such as real-time compression and decompression of video signal is now expected to be the driving force in the evolution of media processor. The MediaSoC322xA consists of two fully programmable processor cores and integrates digital video encoder. The programmable cores toward a particular class of algorithms: the MediaDSP3200 for RISC/DSP oriented functions and multimedia processing, and the RISC3200 for bit stream processing and control function. Dedicated interface units for DRAM, SDRAM, Flash, SRAM, on screen display and the digital video encoder are connected via a 32-bit system bus with the processor cores. The MediaSoC322xA is fabricated in a 0.18um 6LM standard-cell SMIC CMOS technology, occupies about 20mm 2 , and operates at 180MHz. The MeidaSoC322xA are used to audio/video decoder for embedded multimedia application. Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/21/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx SPIE-IS&T/ Vol. 6074 60740D-2 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/21/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

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“…The template was developed based on existing (and proposed) implementations of the applications in our domain. The D30V MPEG multimedia proc~sor [1] and SuperENC [2] (an MPEG-2 video encoder chip) consist of processor cores, dedicated logic and memory elements connected through a single system bus. Hence, MAGELLAN assumes that the system architecture consists of a single bus connected to shared memory and processing elements ( Figure 1).…”

Section: Introductionmentioning

confidence: 99%

Magellan

Chatha

Vemuri

2001

Proceedings of the Ninth International Symposium on Hardware/Software Codesign - CODES '01

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The paper presents MAGELLAN, a heuristic technique for mappin 9 hierarchical control-dataflow task 9raph specifications on heterogeneous architecture templates. The architecture can consist of multiple hardware and software processing elements as specified by the user. The objective of the technique is to minimize the worst ease latency of the task graph subject to the area constraints on the architecture. The technique uses an iterative approach consisting of closely linked hardware-software partitioner and scheduler. Both the partitioner and scheduler operate on the task graph in a hierarchical top down manner. The technique optimizes deterministic loop constructs by applyin 9 clustering, unrollin 9 and pipelinin 9. The technique considers speculative e~eeution for condi. tional constructs. The number of actual hardware/software implementations of a function in the task graph are also optimized by the technique. The effectiveness of the technique is demonstrated by a case study of an image compression algorithm.

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The D30V/MPEG multimedia processor

Cited by 11 publications

References 6 publications

A survey of media processing approaches

A survey of media processing approaches

System-on-chip architecture with media DSP and RISC core for media application

Magellan

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