The Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems

Kazutoshi, Suito; Ueda, Rikuhei; Fujii, Kei; Takuma, Kogo; Matsutani, Hiroki; Yamasaki, Nobuyuki

doi:10.1109/mm.2012.88

Cited by 23 publications

(3 citation statements)

References 10 publications

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“…This necessitates waiting for a whole block of bytes to arrive before performing error correction, introducing latency unacceptable for real-time systems. Retransmission, as noted above, is also not an option as it introduces unbounded latency and, in some cases, makes transmission all but impossible due to exponential decreases in throughput as the bit error rate (BER) increases [8].…”

Section: Introductionmentioning

confidence: 99%

Codeword Set Selection for the Error-Correcting 4b/10b Line Code with Maximum Clique Enumeration

Takeda

Yamasaki

2020

IEICE Trans. Fundamentals

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This paper addresses the problem of finding, evaluating, and selecting the best set of codewords for the 4b/10b line code, a dependable line code with forward error correction (FEC) designed for real-time communication. Based on the results of our scheme [1], we formulate codeword search as an instance of the maximum clique problem, and enumerate all candidate codeword sets via maximum clique enumeration as proposed by Eblen et al. [2]. We then measure each set in terms of resistance to bit errors caused by noise and present a canonical set of codewords for the 4b/10b line code. Additionally, we show that maximum clique enumeration is #P-hard.

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Section: Introductionmentioning

confidence: 99%

Codeword Set Selection for the Error-Correcting 4b/10b Line Code with Maximum Clique Enumeration

Takeda

Yamasaki

2020

IEICE Trans. Fundamentals

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“…We succeeded in packing eleven LSIs into a single 3-cm-square SiP, followed by an even more rigorously scaled 2-cm-square package integrating nine LSIs. However, these packages feature only a single SoC that integrates a multi-threaded processor [10], while multi-processors that consist of multi-core processors are clearly required to meet our high-end real-time processing target. This led us to research and develop a 3D SiP by connecting NoC-based 3D multi-core SoCs through an organic interposer.…”

Section: Introductionmentioning

confidence: 99%

“…Th integrates eleven LSIs including four DR memories, and an SoC (DRMTP [10]) ultrasmall miniaturization requirements as sh To achieve further downscaling for human [11], we implemented a 2-cm-square SiP th LSIs including two DRAMs, two flash mem (D-RMTP) as shown in Fig. 2.…”

Section: Introductionmentioning

confidence: 99%

Three-dimensional packaging structure for 3D-NoC

Wada¹,

Hino²,

Yamasaki

2013

2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS)

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In this paper, we propose a novel threedimensional (3D) packaging structure for a network-on-chip (NoC) based a 3D system-on-chip (SoC). Our SiP is implemented by vertically connecting two homogeneous SoCs through an organic interposer; that is, two homogeneous SoCs are bonded face-to-face above and below the organic interposer. NoCs have routing capability that can communicate with each other even if opposing nodes are connected to different node pins, which enables high-speed communication between SoCs using low voltage and current. As the power supply and external I/O pins are implemented via the organic interposer, we performed simulations to assess power integrity (PI) and signal integrity (SI) compared to a conventional package. To assess vertical communication performance as a 3D package, we simulated high-speed characteristics using the organic interposer and through silicon vias (TSVs), and confirmed the superior performance of the organic interposer.

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