The Dependence of the Performance of Strained NMOSFETs on Channel Width

Yeh, Lingyen; Liao, M.-H.; Chen, Chun Heng; Wu, Jun; Lee, J.Y.-m.; C, Liu; Lee, T.L.; Liang, Mong–Song

doi:10.1109/ted.2009.2030542

Cited by 5 publications

(4 citation statements)

References 15 publications

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“…Stress impact on the device mobility is captured with Japanese Journal of Applied Physics 52 (2013) 04CC20 04CC20-1 # 2013 The Japan Society of Applied Physics REGULAR PAPER http://dx.doi.org/10.7567/JJAP.52.04CC20 R e t r a c t e d model of related strained Si theory. [10][11][12][13][14][15] The dimensions of gate length, gate width, and source/drain (S/D) length of MOSFETs used in this study are 30, 300, and 100 nm, respectively.…”

Section: Device Fabricationmentioning

confidence: 99%

“…8) On the other hand, some other research groups 9) in the company recently found that these mask edge dislocation defects, introduced from amorphization implants and subsequent SPER process, have been shown to induce tensilelike stress in the channel of the Si transistor resulting in N-type metal-oxide-semiconductor field-effect transistors (N-MOSFETs) mobility enhancement, based on the strained Si theory. [10][11][12][13][14][15] However, the detailed mechanism for the root cause of tensile-like stress in the channel by SPER process and a numeric model for the mask dislocation edge stress are still not clear and lacked. In this work, the atomic force microscope AFM-Raman technique with the nanometer (nm) level space resolution to extract the channel stress in the real transistor dimension is carried out firstly.…”

Section: Introductionmentioning

confidence: 99%

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Optimization of Dislocation Edge Stress Effects for Si N-Type Metal–Oxide–Semiconductor Field-Effect Transistors

Liao

Chen

Chang

et al. 2013

Jpn. J. Appl. Phys.

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The comprehensive investigation on the effect of dislocation edge stress for Si N-type metal–oxide–semiconductor field-effect transistors (N-MOSFETs) is presented in this work by the experimental measurement and proposed simulation model. The accurate stress measurement in Si oxide dimension (OD) region with and without dislocation edge stress treatment is extracted by atomic force microscope (AFM)–Raman technique with the nanometer level space resolution. Less compressive stress in Si OD region on the real transistor with dislocation edge stress treatment is observed successfully and has its corresponding higher electron carrier mobility, agreed with the strained Si theory. Main reasons for the less compressive stress in the device with dislocation edge stress treatment are the more stress relaxation of the shallow trench insulator (STI) intrinsic compressive stress in modern CMOS process and one layer Si atom missing near the source and drain region along the dislocation line. The measured stress from AFM–Raman spectra experimentally, the simulated stress from proposed finite element method, and its corresponding electrical characteristics agrees well with each other in this work. After the comprehensive understanding and calibrated model for the dislocation edge stress, the relationship between channel stress and dislocation edge shapes, including the angle and length of dislocation lines, is simulated and investigated clearly. It can be found that longer dislocation line and smaller dislocation angle can relax the intrinsic STI compressive stress more and should have the better electron carrier mobility and device performance for N-MOSFETs.

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Section: Device Fabricationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Optimization of Dislocation Edge Stress Effects for Si N-Type Metal–Oxide–Semiconductor Field-Effect Transistors

Liao

Chen

Chang

et al. 2013

Jpn. J. Appl. Phys.

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“…Most of previous literature that simulated stress distributions within nano scaled devices only considered eventual configurations. 4,5) Those advanced semiconductor materials, such as Ge and Group III-V elements, have native superior carrier mobilities but also poor thermal conductivity interpreted from individual band structure. Consequently, the measurements and discussions of thermo-physical characteristics regarding the abovementioned materials were studied.…”

mentioning

confidence: 99%

Performance characteristics of strained Ge p-FinFETs under the integration of lattice and self-heating stress enabled by process-oriented finite element simulation

Lee

Hsieh

Huang

et al. 2021

Appl. Phys. Express

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Stress-induced mechanism and related manifold characteristics from lattice mismatch and harsh self-heating effect (SHE) substantially interact are major concerns of advanced strained Ge p-FinFETs with inherent poor thermal conductivity. This study presents a process-oriented simulation methodology to investigate the comprehensive influences composed of the stress amplitude and performance variations induced by SHE and lattice stresses. Device performance can be separately improving by 15.98% and 31.20% when lattice strain and subsequent SHE are introduced. In conclusion, the effect of SHE on the performance of advanced p-FinFET is explored and found tantamount to the stress contribution of the lattice mismatch.

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“…9 and the theoretical calculation on the electron mobility dependency with the channel stress from our work in Ref. [10][11][12]. With the calibration among measured stress data by AFM-Raman, simulated stress value by finite element method, and its corresponding electrical characteristics, the full simulated model on the characteristics of transistor with the dislocation edge stress treatment are created and provided successfully.…”

mentioning

confidence: 99%

The investigation on Dislocation Edge Stress Effects for Si N-MOSFETs

Liao¹,

Chen²,

Chang³

et al. 2012

Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials

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Introduction Single-directional Solid Phase Epitaxial Re-growth (SPER) process of amorphous Si has been a topic of fundamental and technological importance for several decades since first being reported more than 40 years ago [1, 2]. The roles of growth temperature [3], substrate orientation [4], and impurities [5] had also been widely studied with more investigation of these effects of stress on the single-directional SPER process [6]. In addition to the single-directional process, Dr. Morarka and Dr. Rudawski has also studied and reviewed the two-dimensional (2D) SPER process recently [7, 8], because SPER process must be considered as multi-directional rather than bulk in nature with the evolving growth interface having multiple crystallographic orientations in the modern patterned device processing. For the 2D SPER process, the relative differences in the velocity of re-growth fronts with different multiple crystallographic orientations and intrinsic stress induced from the typical Si-based device fabrication will lead to the formation of device mask edge defects [7]. The experimental data show that the stress generated in the Si substrate from the patterning, both in line and square structures, alters the kinetics and geometry of the multi-directional SPER process, and can influence the formation of mask edge defects which form during the growth to different degrees as per difference in the substrate stresses generated by each type of patterning [8]. On the other hand, some other research groups [9] in the company recently found that these mask edge dislocation defects, introduced from amorphization implants and subsequent SPER process, have been shown to induce tensile-like stress in the channel of the Si transistor resulting in NMOSFETs mobility enhancement, based on the strained Si theory [10-12]. However, the detailed mechanism for the root cause of tensile-like stress in the channel by SPER process and a numeric model for the mask dislocation edge stress are still unclear and lacked. In this work, the AFM-Raman technique with the nanometer (nm) level space resolution to extract the channel stress in the real transistor dimension is carried out firstly. Secondly, the measured stress is compared with the simulation model by the proposed finite element method in this work to evaluate realistic devices with surfaces and material interfaces. After the calibration and the agreement between simulation data and experimental electrical characteristics of the real transistor, the physical origin and simulated model for the dislocation edge stress on the real application for the transistor performance booster have been understood and given, respectively. Finally, the optimal dislocation shape, including dislocation length and angle, is also discussed

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The Dependence of the Performance of Strained NMOSFETs on Channel Width

Cited by 5 publications

References 15 publications

Optimization of Dislocation Edge Stress Effects for Si N-Type Metal–Oxide–Semiconductor Field-Effect Transistors

Optimization of Dislocation Edge Stress Effects for Si N-Type Metal–Oxide–Semiconductor Field-Effect Transistors

Performance characteristics of strained Ge p-FinFETs under the integration of lattice and self-heating stress enabled by process-oriented finite element simulation

The investigation on Dislocation Edge Stress Effects for Si N-MOSFETs

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