The dependence of UMOSFET characteristics and reliability on geometry and processing

Abstract

We have examined the impact of trench processing and trench and device cell geometries on the characteristics of a single n-channel U-shaped trench metal-oxide-silicon field-effect transistor (n-UMOSFET) and a device cell comprising several n-UMOSFETs. The geometrical parameters investigated included the trench depth and width, the trench cross-section and the device cell pitch. We have found out that the geometry does not affect the electron mobility in the channel; however, the effects of the geometry on the characteristics of the isolated device or device cell are manifested on the spreading resistance of the drain end. Trench processing, in the form of trench etching, trench cleaning and subsequent gate-oxide growth, is observed to primarily influence the n-UMOSFET's immunity to electrical stress, which is studied using charge pumping current and gate-oxide breakdown measurements. It is shown that the gate-oxide edge adjacent to the drain and the oxide/silicon interface overlapping the drain are the regions most susceptible to degradation by Fowler-Nordheim stress. These observations coupled with results from scanning electron microscopy suggest that the gate-oxide growth non-uniformity as well as its condition at the trench corners are the key factors in determining the n-UMOSFET's reliability.

A model for avalanche breakdown calculation in low-voltage trench power MOSFET devices

“…The structure changes from a diode to a trench-type MOSFET [14]. The structure modification affects the breakdown characteristics of the p + -n diode (now bodydrain junction) due to the shift of the maximum electric field position from the p + -n junction to the trench edge [15][16][17]. Therefore, the electric field on the body-drain junction will not reach the critical value expressed in formula (3).…”

Static and dynamic electrical performances of STI thin-SOI power LDMOS transistors

“…The STI LDMOS transistor requires a previously formed STI block in the drift region by means of RIE dry etching, sacrificial oxide growth and etching in order to remove the impurities distributed at the surface of the trench sidewall and to improve the trench surface. In fact, different techniques [8,16] are applied with the purpose of smoothing the bottom corner in the trench which is desirable to minimize the electric field stress. A dry oxide growth is followed by oxide deposition and planarization by chemical mechanical polishing (CMP).…”

“…A second approach is the cell-pitch reduction which is done by placing an oxide trench in the LDMOS drift region to have quasi-vertical conduction and to improve the R ON-sp /V BR trade-off [5][6][7]. This solution requires precise trench technology since the condition and the geometry of the trench, especially the trench corners, can significantly influence the performance and reliability of the device [8].…”

High-Temperature Reverse-Bias Stressing of Thin Gate Oxides in Power Transistors

“…In this work HTRB was found to generate negative-bias temperature instabilities (NBTI) in a parasitic p-channel MOSFET (P-MOSFET) occurring in an N-channel UMOSFET (N-UMOSFET) during the stress (4,5). We also employ Fowler-Nordheim (FN) stress and examine the condition of the gate oxide and oxide/Si interface at the bottom of the trench adjacent to the drain in the N-UMOSFET (6).…”