The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture

Noda, Haruhiko; Nakajima, M.; Dosaka, K.; Kiyoshi, Nakata; Higashida, M.; Yamamoto, Osamu; Mizumoto, K.; Tanizaki, T.; Gyohten, T.; Okuno, Y.; Kondo, Hiroyuki; Shimazu, Y.; Arimoto, Kazutami; Saito, Kazunori; Shimizu, Toshihisa

doi:10.1109/jssc.2006.886545

Cited by 21 publications

(10 citation statements)

References 8 publications

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“…The height and width of the PEs are not decided by the transistor number but by the required routing area for H-ch and V-ch, respectively. Because the layout pitch in the H-ch direction is doubled for the 2-bit PE [1], the height of the 4-bit and 2-bit PE remains the same. However, the 4-bit PE needs to be twice as wide as the 2-bit PE in order to accommodate the expansion of the bit width of V-ch.…”

Section: A 4-bit Processing Elementmentioning

confidence: 99%

“…There are many applications for these devices, and the advancement of processing algorithms is much faster than the development cycle of system-on-a-chip (SoC) hardware solutions. Therefore, the usage of programmable image processors has recently been increasing [1]- [5]. An image processor requires high power efficiency for long battery life and needs to be able to operate reliably under high temperature conditions.…”

Section: Introductionmentioning

confidence: 99%

“…However, the performances required are different for each application, so scalability of the number of PEs is necessary to realize power and area efficiency. Our previous work on a flexible matrix processor (MTX) [1] achieved both high power efficiency and high area efficiency. Fig.…”

Section: Introductionmentioning

confidence: 99%

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A Scalable Massively Parallel Processor for Real-Time Image Processing

Kurafuji

Haraguchi

Nakajima

et al. 2011

IEEE J. Solid-State Circuits

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This paper describes a high performance scalable massively parallel single-instruction multiple-data (SIMD) processor and power/area efficient real-time image processing. The SIMD processor combines 4-bit processing elements (PEs) with SRAM on a small area and thus enables at the same time a high performance of 191 GOPS, a high power efficiency of 310 GOPS/W, and a high area efficiency of 31.6 GOPS/mm . The applied pipeline architecture is optimized to reduce the number of controller overhead cycles so that the SIMD parallel processing unit can be utilized during up to 99% of the operating time of typical application programs. The processor can be also optimized for low cost, low power, and high performance multimedia system-on-a-chip (SoC) solutions. A combination of custom and automated implementation techniques enables scalability in the number of PEs. The processor has two operating modes, a normal frequency (NF) mode for higher power efficiency and a double frequency (DF) mode for higher performance. The combination of high area efficiency, high power efficiency, high performance, and the flexibility of the SIMD processor described in this paper expands the application of real-time image processing technology to a variety of electronic devices.Index Terms-Image processor, power efficiency, area efficiency, SIMD, scalable architecture, fine grained processing element.

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Section: A 4-bit Processing Elementmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Scalable Massively Parallel Processor for Real-Time Image Processing

Kurafuji

Haraguchi

Nakajima

et al. 2011

IEEE J. Solid-State Circuits

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“…The MX is a SIMD (Single Instruction, Multiple Data) massively parallel processor [2], which is specialized to process a large amount of image data. The MX has 640 processing elements of 2bits each, a 32kB instruction memory, and an 80kB data memory with a four-bank configuration.…”

Section: B General-purpose Acceleratormentioning

confidence: 99%

Heterogeneous multicore SoC for secure multimedia applications

Kondo

Nakajima

Otani

et al. 2008

2008 IEEE Custom Integrated Circuits Conference

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A heterogeneous multicore SoC (System on a Chip) has been developed for HD (High-Definition) multimedia applications that require secure DRM (Digital Rights Management). The SoC integrates three types of processors: two specific-purpose accelerators for a cipher and a high-resolution video decoding; one general-purpose accelerator (MX: Matrix processor); and three CPUs. This is how our SoC achieves high performance and low power consumption with hardware customized for video processing applications that process a large amount of data. To achieve secure data control, hardware memory management and software system virtualization are adopted. The security of the system is the result of the cooperation between the hardware and software on the system. Furthermore, a highly tamper-resistant system is provided on our SiP (System in a Package), through DDR memories and Flash ROM that contain confidential information in one package. This secure multimedia processor provides a solution to protect contents and to safely deliver secure sensitive information when processing billing transactions that involve digital content delivery. The SoC was implemented in the 90nm generic CMOS technology.

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“…Several parallel processing architectures have been presented for vision applications. Massively parallel single-instructionmultiple-data (MP-SIMD) processors with linear processor array, such as Internet message access protocol [8] and Xetal [9] have been developed for low-level vision processing [10], [11]. However, these processors are not suitable for higher-level vision applications that exhibit more irregular and data-dependent behavior than low-level operations.…”

mentioning

confidence: 99%

A Configurable Heterogeneous Multicore Architecture With Cellular Neural Network for Real-Time Object Recognition

Kim

Lee

Kim

et al. 2009

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-As object recognition requires huge computation power to deal with complex image processing tasks, it is very challenging to meet real-time processing demands under low-power constraints for embedded systems. In this paper, a configurable heterogeneous multicore architecture with a dual-mode linear processor array and a cellular neural network on the networkon-chip platform is presented for real-time object recognition. The bio-inspired attention-based object recognition algorithm is devised to reduce computational complexity of the object recognition. The cellular neural network is utilized to accelerate the visual attention algorithm for selecting salient image regions rapidly. The dual-mode parallel processor is configured into single instruction, multiple data (SIMD) or multiple-instructionmultiple-data modes to perform data-intensive image processing operations while exploiting pixel-level and feature-level parallelisms required for the attention-based object recognition. The algorithm's hybrid parallelization strategy on the proposed architecture is adopted to obtain maximum performance improvement. The performance analysis results, using a cycle-accurate architecture simulator, show that the proposed architecture achieves a speedup of 2.8 times for the target algorithm over conventional massively parallel SIMD architecture at low hardware cost overhead. A prototype chip of the proposed architecture, fabricated in 0.13 µm complementary metal-oxidesemiconductor technology, achieves 22 frames/s real-time object recognition with less than 600 mW power consumption.

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The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture

Cited by 21 publications

References 8 publications

A Scalable Massively Parallel Processor for Real-Time Image Processing

A Scalable Massively Parallel Processor for Real-Time Image Processing

Heterogeneous multicore SoC for secure multimedia applications

A Configurable Heterogeneous Multicore Architecture With Cellular Neural Network for Real-Time Object Recognition

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