The design of a low energy FPGA

George, Varghese; Zhang, Hui; Rabaey, Jan M.

doi:10.1145/313817.313920

Cited by 93 publications

(5 citation statements)

References 9 publications

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“…A small binary tree and inverse clustering network are shown in Figure 5.2. The inverse clustering network is described in [52] and is essentially a rearrangement of the binary tree so that clusters that are farther away from each other are connected with shorter paths. This has the effect of reducing the delay and energy through these paths because long distance traveling packets no longer need to pass through a large number of routers and in the case of CMOS IC implementations, can be routed through lower metal layers.…”

Section: Tree and Inverse Clusteringmentioning

confidence: 99%

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Energy-Efficient Multipath Ring Network for Heterogeneous Clustered Neuronal Arrays

Ardelean

2022

Real-Time Multi-Chip Neural Network for Cognitive Systems

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Simulating large spiking neural networks (SNN) with a high level of realism in a field programmable gate array (FPGA) requires efficient network architectures that satisfy both resource and interconnect constraints, as well as changes in traffic patterns due to learning processes. Based on a clustered SNN simulator concept, in this thesis, an energyefficient multipath ring network topology is presented for the neuronto-neuron communication. It is compared in terms of its mathematical properties with other common network topology graphs after which the traffic distributions across it and a two dimensional torus network are estimated and contrasted. As a final characterization step, the energy-delay product of the multipath topology is estimated and compared with other low power architectures. In addition, a simplified

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Section: Tree and Inverse Clusteringmentioning

confidence: 99%

“…Inverse clustering with mesh is a hybrid architecture proposed in [52] that, as the name suggests, uses a mesh to connect neighboring clusters and the inverse clustering for longer paths. Figure 5.3 shows an example of such a topology for a network of 16 clusters.…”

Section: Inverse Clustering With Meshmentioning

confidence: 99%

Energy-Efficient Multipath Ring Network for Heterogeneous Clustered Neuronal Arrays

Ardelean

2022

Real-Time Multi-Chip Neural Network for Cognitive Systems

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“…The authors in [72][73] have described energy-efficient FPGA routing architectures and low-swing signaling techniques to reduce power, whereas, a new FPGA routing architecture that utilizes a mixture of hardwired and traditional programmable switches is proposed In [74] , which reduces static and dynamic power by reducing the number of configurable routing elements. The architecture and the circuit-level implementation of the FPGA is key in reducing power, since it directly affects the efficiency of mapping applications to FPGA resources, and the amount of circuitry to implement these resources.…”

Section: Power Reduction At Architecture-and Circuitlevel Designmentioning

confidence: 99%

Reduction of Power Consumption in FPGAs - An Overview

Grover¹,

Soni²

2012

IJIEEB

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-Field Programmable Gate Arrays FPGAs are highly desirable for implementation of digital systems due to their flexibility, programmability and low end product life cycle. In more than 20 years since the introduction of FPGA, research and development has produced dramatic improvements in FPGA speed and area efficiency, narrowing the gap between FPGAs and ASICs and making FPGAs the platform of choice for implementing digital circuits. FPGAs hold significant promise as a fast to market replacement. Unfortunately, the advantages of FPGAs are offset in many cases by their high power consumption and area. The goal is to reduce the power consumption without sacrificing much performance or incurring a large chip area so that the territories of FPGAs applications can expand more effectively. Reducing the power of FPGAs is the key to lowering packaging and cooling costs, improving device reliability, and opening the door to new markets such as mobile electronics. This paper presents the tips to lower down the static and dynamic power dissipation in FPGAs. It gives an overview of various techniques at system, device, and circuit and architecture level used for reduction of power consumption of FPGAs and their outcomes.

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“…The study described in [George 1999] examines the design of energy efficient FPGAs. For clock networks, the study proposes that edge triggered flip-flops are used within logic blocks to reduce the power dissipated by the clock network, since this reduces the toggle rates by a factor of two.…”

Section: Previous Workmentioning

confidence: 99%

On the trade-off between power and flexibility of FPGA clock networks

Lamoureux

Wilton

2008

ACM Trans. Reconfigurable Technol. Syst.

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________________________________________________________________________FPGA clock networks consume a significant amount of power since they toggle every clock cycle and must be flexible enough to implement the clocks for a wide range of different applications. The efficiency of FPGA clock networks can be improved by reducing this flexibility; however, reducing the flexibility introduces stricter constraints during the clustering and placement stages of the FPGA CAD flow. These constraints can reduce the overall efficiency of the final implementation. This paper examines the tradeoff between the power consumption and flexibility of FPGA clock networks.Specifically, this paper makes three contributions. First, it presents a new parameterized clock network framework for describing and comparing FPGA clock networks. Second, it describes new clock-aware placement techniques that are needed to find a legal placement that satisfies the constraints imposed by the clock network. Finally, it performs an empirical study to examine the tradeoff between the power consumption of the clock network and the impact of the CAD constraints for a number of different clock networks with varying amounts of flexibility.The results show that the techniques used to produce a legal placement can have a significant influence on power and the ability of the placer to find a legal solution. On average, circuits placed using the most effective techniques dissipate 5% less overall energy and were significantly more likely to be legal than circuits placed using other techniques. Moreover, the results show that the architecture of the clock network is also important. On average, FPGAs with an efficient clock network were up to 14.6% more energy efficient compared to other FPGAs. Permission to make digital/hard copy of part of this work for personal or classroom use is granted without fee provided that the copies are not made or distributed for profit or commercial advantage, the copyright notice, the title of the publication, and its date of appear, and notice is given that copying is by permission of the ACM, Inc. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or a fee. © 2008 ACM 1073-0516/01/0300-0034 $5.00Designing a suitable clock distribution network for an FPGA is significantly more challenging than designing such a network for a fixed function chip such as an Application-Specific Integrated Circuit (ASIC). In an ASIC, the locations and skew requirements of each domain are known when the clock network is designed. In an FPGA, however, a single clock network that works well across many applications must be created. When the FPGA is designed, the number of clock domains the user will require, the clock signals that will be generated, the skew requirements of each domain, and where each domain will be located on the chip are all unknown. This forces FPGA vendors to create very complex yet flexible clock distribution circuitry.This flexibility has a significant area a...

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The design of a low energy FPGA

Cited by 93 publications

References 9 publications

Energy-Efficient Multipath Ring Network for Heterogeneous Clustered Neuronal Arrays

Energy-Efficient Multipath Ring Network for Heterogeneous Clustered Neuronal Arrays

Reduction of Power Consumption in FPGAs - An Overview

On the trade-off between power and flexibility of FPGA clock networks

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