The Design of Digital Sub-array Synchronization for Phased Array Radar

Guan, Yaping; Wang, Yi; Ji, Shuai

doi:10.1109/apcap50217.2020.9245993

Cited by 3 publications

(1 citation statement)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The JESD204 protocol, proposed by JEDEC, has gradually replaced CMOS and LVDS as the mainstream data transmission solution between converter devices and logic devices [32]. Researchers have achieved multi-channel data transmission alignment by utilizing the system reference edge [33] and the deterministic latency characteristics of the JESD204B/C protocols [34][35][36]. In addition, some researchers have alleviated the pressure of synchronous design by integrating converters and radio frequency components [37][38][39].…”

Section: Introductionmentioning

confidence: 99%

Pulse Compression Shape-Based ADC/DAC Chain Synchronization Measurement Algorithm with Sub-Sampling Resolution

Hao,

Fang,

Luo

et al. 2024

Sensors

View full text Add to dashboard Cite

In this article, we address the problem of synchronizing multiple analog-to-digital converter (ADC) and digital-to-analog converter (DAC) chains in a multi-channel system, which is constrained by the sampling frequency and inconsistencies among the components during system integration. To evaluate and compensate for the synchronization differences, we propose a pulse compression shape-based algorithm to measure the entire delay parameter of the ADC/DAC chain, which achieves sub-sampling resolution by mapping the shape of the discrete pulse compression peak to the signal propagation delay. Moreover, owing to the matched filtering in the pulse compression process, the algorithm exhibits good noise performance and is suitable for wireless scenarios. Experiments verified that the algorithm can achieve precise measurements with sub-sampling resolution in scenarios where the signal-to-noise ratio (SNR) is greater than −10 dB.

show abstract