The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

Bindal, Ahmet; Naresh, Anyam; Yuan, Pigen; Nguyen, Khanh; Hamedi-Hagh, Sotoudeh

doi:10.1109/tnano.2007.894355

Cited by 16 publications

(8 citation statements)

References 54 publications

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“…signal characterization of a 50 nm gate FinFET measurement has predicted the maximum oscillation frequency of 250 GHz with an optimized fabrication process [22]. Among the nanoscale multiple-gate devices, the silicon-based nanowire FETs have the ultimate gate structures and become potential candidates for next-generation high-speed and high-power electronic devices [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27]. Besides the perfect channel controllability resulting from the nature of the gate-all-around channel [19][20][21], the nanowire FETs may tolerate having a thicker silicon fin, compared with double-and triplegate FinFETs according to the manufacturability point of view [20,21].…”

Section: Introductionmentioning

confidence: 99%

DC baseband and high-frequency characteristics of a silicon nanowire field effect transistor circuit

Li¹,

Hwang²

2009

Semicond. Sci. Technol.

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Silicon-based nanowire field effect transistors (FETs) are potentially next-generation candidates for achieving high-performance targets of the International Roadmap for Semiconductors due to their superior reduction of the short-channel effects and excellent compatibility with planar complementary metal oxide semiconductor (CMOS) fabrication process. In this work, we for the first time numerically explore the dc baseband and high-frequency characteristics, and the design of the device aspect ratio (channel length/channel thickness) for the silicon nanowire FET circuits by using a three-dimensional device/circuit-coupled mixed-mode simulation technique. With the experimentally validated simulation approach, the result shows the rather prolific dc baseband and high-frequency properties of silicon-based nanowire FET devices as active components. In design of silicon nanowire FETs, taking the nanowire's radius and channel length as two crucial factors, the demands of the device aspect ratio on dc characteristics are found to be inversely proportional to the demands of the high-frequency characteristics. Therefore, to compromise both the dc and high-frequency characteristics, the design margin of the device aspect ratio restricted, in which the requirements of dc and high-frequency characteristics provide aspect ratio upper and lower bounds, respectively. Moreover, the design margin will be more tightened for a device with larger radius due to the weakened channel controllability. The extensive results and analyses are presented for the promising devices for the design of high-frequency analog applications.

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Section: Introductionmentioning

confidence: 99%

DC baseband and high-frequency characteristics of a silicon nanowire field effect transistor circuit

Li¹,

Hwang²

2009

Semicond. Sci. Technol.

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“…To build the CMOS configuration it is easier to use the top-down process technology for implementation. PFET and NFET conductance matching by width, like CMOS design, is not possible for single-diameter NW, and two p-type wires for one n type [6] or different diameters for p-type and n-type NWFETs are proposed [7].…”

Section: Inverter and Logic Gate Configurationmentioning

confidence: 99%

Nanowire FET Circuit Design: An Overview

Chung

2013

Nanowire Field Effect Transistors: Principles and Applications

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Thanks to the short-channel effect suppression of nanowire FET (NWFET), it has become a candidate for the next-generation VLSI device. Different types of NWFETs are introduced to meet the system requirements, with pros and cons. The bottom-up-processed transistor provides the full performance in transistor level, but the integration capability is bounded by the single type of devices per layer and logic design for NMOS and PMOS combined structure is severely restricted. Besides, gate length is relatively large sized, and to overcome this, crossed nanowire transistor-based nanoscale integrated circuit (NASIC) is proposed. Even though this design achieves the minimum area and promises for the large-scale integration so far, the transistor performance is far from the nanotransistor, because of its nonclosed gate structure. Top-down process allows flexible design, but the performance and integration are in its early stage. CMOS interface is required to activate the NW logic and to provide signals from/to conventional system. Abbreviation NWFET

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“…Therefore, alternative silicon compatible transistor devices such as silicon on insulator (SOI) MOSFETs, FinFETs, and nanotube FETs have been investigated for improved performance [2].…”

Section: Introductionmentioning

confidence: 99%

Design and Characterization of the Next Generation Nanowire Amplifiers

Hamedi-Hagh

Bindal

2008

VLSI Design

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Vertical nanowire surrounding gate field effect transistors (SGFETs) provide full gate control over the channel to eliminate shortchannel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10 nm channel length and a 2 nm channel radius. The amplifier dissipates 5 μW power and provides 5 THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V, and a distortion better than 3% from a 1.8 V power supply and a 20 aF capacitive load. The 2nd-and 3rd-order harmonic distortions of the amplifier are −40 dBm and −52 dBm, respectively, and the 3rd-order intermodulation is −24 dBm for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high-speed analog and VLSI technologies.

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The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

Cited by 16 publications

References 54 publications

DC baseband and high-frequency characteristics of a silicon nanowire field effect transistor circuit

DC baseband and high-frequency characteristics of a silicon nanowire field effect transistor circuit

Nanowire FET Circuit Design: An Overview

Design and Characterization of the Next Generation Nanowire Amplifiers

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