The Design of Fault Tolerant PSTR Using Virtualization Techniques on the Embedded System

Abstract

This paper is a study related to fault tolerant design based on PSTR using virtualization techniques. If the fault tolerant PSTR based on virtualization techniques is implemented the communication performance between primary and shadow will improves and monitoring function is easy to available about activities of primary and shadow. The legacy PSTR model is implemented in its hardware. The primary play a main role and shadow play a switched action when the errors occurrs in the primary. The switched action of shadow make it possible to restart the primary function newly. This paper implements fault tolerant primary-shadow model using virtualization techniques on the embedded environment.

Research on Fault-Tolerant Technology of Embedded Computer Control System

“…The computer hardware composition block diagram is shown in Fig.1, which mainly contains five components: control hostcmputer, peripheral equipments, input and output channel, interface circuit and operating platform [9]. [10]. In the computer control system, each controlled object or controlling task needs to be equipped with corresponding control programs, which are used to satisfy different requirements of controlled objects.…”