The design of high-performance microprocessors at Digital

Fox, T.F.

doi:10.1145/196244.196570

Cited by 6 publications

(3 citation statements)

References 6 publications

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“…The CAD tools used on this chip were largely the same as those used on our Alpha designs. 5 This is not surprising since the performance target of the chip roughly parallels that of the Alpha family as noted in the section Circuit Implementation. The most significant departure was in the area of static timing verification and race analysis where the adoption of edge-triggered latching required significant modifications to the tools used in the Alpha designs.…”

Section: Cad Toolsmentioning

confidence: 85%

A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor

Montanaro

Witek

Anne

et al. 1996

IEEE J. Solid-State Circuits

456

125

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This paper describes a 160 MHz 500 mW StrongARM microprocessor designed for lowpower, low-cost applications. The chip implements the ARM V4 instruction set 1 and is bus compatible with earlier implementations. The pin interface runs at 3.3 V but the internal power supplies can vary from 1.5 to 2.2 V, providing various options to balance performance and power dissipation. At 160 MHz internal clock speed with a nominal Vdd of 1.65 V, it delivers 185 Dhrystone 2.1 MIPS while dissipating less than 450 mW. The range of operating points runs from 100 MHz at 1.65 V dissipating less than 300 mW to 200 MHz at 2.0 V for less than 900 mW. An on-chip PLL provides the internal clock based on a 3.68 MHz clock input. The chip contains 2.5 million transistors, 90% of which are in the two 16 kB caches. It is fabricated in a 0.35-m three-metal CMOS process with 0.35 V thresholds and 0.25 m effective channel lengths. The chip measures 7.8 mm ϫ 6.4 mm and is packaged in a 144-pin plastic thin quad flat pack (TQFP) package.

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Section: Cad Toolsmentioning

confidence: 85%

A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor

Montanaro

Witek

Anne

et al. 1996

IEEE J. Solid-State Circuits

456

125

View full text Add to dashboard Cite

show abstract

“…5 This is not surprising since the performance target of the chip roughly parallels that of the Alpha family as noted in the section Circuit Implementation. The most significant departure was in the area of static timing verification and race analysis where the adoption of edge-triggered latching required significant modifications to the tools used in the Alpha designs.…”

Section: Cad Toolsmentioning

confidence: 85%

A 200 MHz 32 b 0.5 W CMOS RISC microprocessor

Stephany¹,

Anne²,

Bell³

et al.

1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)

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IntroductionAs personal digital assistants (PDA's) move into the next generation, there is an obvious need for additional processing power to enable new applications and improve existing ones. While enhanced functionality such as improved handwriting recognition, voice recognition, and speech synthesis are desirable, the size and weight limitations of PDA's require that microprocessors deliver this performance without consuming additional power. The microprocessor described in this paper-the Digital Equipment Corporation SA-110, the first microprocessor in the StrongARM family-directly addresses this need by delivering 185 Dhrystone 2.1 MIPS while dissipating less than 450 mW. This represents a significantly higher performance than is currently available at this power level. CMOS Process TechnologyThe chip is fabricated in a 0.35 m three-metal CMOS process with 0.35 V thresholds and 0.25 µm effective channel lengths. Process characteristics are shown in Table 1. The process is the result of several generations of development efforts directed toward highperformance microprocessors. It is identical to the one used in Digital Equipment Corporation's current generation of Alpha chips 2 except for the removal of the fourth layer of metal and the addition of a final nitride passivation required for plastic packaging.The factors which drive process development for low-power design are similar to those which drive the process for pure high-performance although the motivation sometimes differs. For example, while both types of designs benefit from maximizing Idsat of the transistors at the lowest acceptable Vdd, the motivation for a pure high-performance design is reducing power distribution and thermal problems rather than extending battery life. Similar arguments apply to minimizing transistor leakage and on-chip variation of transistor parameters. This convergence of goals has been essential to our ability to develop one process to satisfy the requirements of both low-power and high-performance families.

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“…Finally, the design and implementation of a complex, performance-critical device like Drishti with all the challenges described above and the need to meet tight market windows requires an efficient concurrent design process rather than a traditional sequential design approach [6,7]. It is essential that verification be performed in concurrence with design-space explorations involving area, delay, power, testability, reliability, pinout and package.…”

Section: Motivationmentioning

confidence: 99%

Challenges in the design of a scalable data-acquisition and processing system-on-silicon

Karanth

Sarkar²,

Venkatraman³

et al.

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conferen

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Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements bring in several challenges into the design of present day VLSI chips. In this paper we present the challenges faced and the approaches successfully adopted in the design of a complex 2.5 million gate high bandwidth data acquisition and processing VLSI chip (a trace-receiver chip, code-named Drishti) in a deep sub-micron technology at Texas Instruments India. The very high design complexity arises due to the rich architecture of the trace-receiver chip, the aggressive timing and performance requirements and its large size. The trace-receiver chip is highly configurable and scalable, thereby catering to both low-end systems, which are cost sensitive, and high-end applications, which demand performance. We present the innovative approaches that were applied to address the challenges encountered in meeting the aggressive design goals (which include functionality, timing, testability, manufacturability, reliability, system issues etc) and to bring the product early to market. Efficient logical and physical partitioning, design reuse and DFT strategies are a few of the techniques that were applied in this design. We present these along with details on the various analyses carried out as part of the design, including signal-integrity, reliability and system-level analyses, which were very critical in ensuring design-closure.

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The design of high-performance microprocessors at Digital

Cited by 6 publications

References 6 publications

A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor

A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor

A 200 MHz 32 b 0.5 W CMOS RISC microprocessor

Challenges in the design of a scalable data-acquisition and processing system-on-silicon

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