The design of parallelized BCH codec

Wang, Chenxu; Gao, Yang; Han, Liang; Wang, Jinxiang

doi:10.1109/cisp.2010.5646178

Cited by 2 publications

(2 citation statements)

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“…Typically, the encoder is implemented as a linear feedback shift register (LFSR) where the coefficients of g ( x ) represent the taps of the feedback [4, 16–18]. However, for the decoding of the GC code, we require a fast encoding procedure, because the encoder is active in every re‐encoding step.…”

Section: Code Componentsmentioning

confidence: 99%

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Decoder architecture for generalised concatenated codes

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Freudenberger

2015

IET Circuits, Devices & Systems

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This paper proposes a pipelined decoder architecture for generalised concatenated (GC) codes. These codes are constructed from inner binary Bose-Chaudhuri-Hocquenghem (BCH) and outer Reed-Solomon codes. The decoding of the component codes is based on hard decision syndrome decoding algorithms. The concatenated code consists of several small BCH codes. This enables a hardware architecture where the decoding of the component codes is pipelined. A hardware implementation of a GC decoder is presented and the cell area, cycle counts as well as the timing constraints are investigated. The results are compared to a decoder for long BCH codes with similar error correction performance. In comparison, the pipelined GC decoder achieves a higher throughput and has lower area consumption.

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Section: Code Componentsmentioning

confidence: 99%

“…In order to decode a received word r ( x ), first the syndrome S ( x ) is calculated by processing the entire received word r ( x )

S_{i} = r false(α^{i + 1} false), i = 0, \dots, 2 t - 1

Similar to the encoder, the syndrome calculation is usually implemented using an LFSR [4, 17, 18]. Again, we use a direct implementation that requires only one cycle.…”

Section: Code Componentsmentioning

confidence: 99%