The design of the high speed amplifier circuit for using in the analog subsystems

Abstract

In tbis paper, a high speed CMOS amplifier circuit has been desi@ and applicated in high speed simple CMOS comparator. The designed CMOS amplifier circuit has a new architecture for using in high speed analog subsystem circuits. This new architecture composed with interrul b i i circuits and CMOS complementary gain stage can be improved gain and speed characteristics. And also.we has been designed a high speed simple CMOS comparator using improved CMOS amplifier circuit with a standard 1.5@] processing parameter. This circuit can be operated in a few nano second.

Novel 1.25Gb/s CMOS burst mode optical receiver with automatically gain controllable preamplifier and high sensitive peak detector without external reset signal

“…Therefore, even though it takes much time to discharge the peak holding capacitor, it is not a matter if that time satisfies the given specifications by controlling the gate voltage of the Q 15 . The output of the envelope detector is input to the high-speed comparator [8], and compares the envelope detector output with predetermined voltage which is indicated "Cont" node in Figure 8 (b). Then, we can get the reset signal and inverted reset signal by the next two inverters.…”