The design of the M3S: a multiported shared-memory multiprocessor

Abstract

M3S is an academic shared-memory multiprocessor.The memory is divided into modules. Each processor (through its cache) has an access to each memory module only through a high-throughput private serial link, Each memory module has several serial ports lhat are connected, in parallel, to the memory. The data coherency is maintained by a hardware direclory-based scheme.The interconnection network has no bottleneck since each processor has its private path to each memory module. The high bit rate of the serial links is the most important technical problem for the design of this proiorype. Synchronous solurions have been chosen inthe prototype because of their greater simplicity. The data rate on the serial links is 800 Mbitls. We explain. in this paper, different choices we have mude to realize rhis project with one memory module and sixteen processor modules.