The design revolution of logarithmic number system architecture

Naziri, Siti Zarina Md; Ismail, Rizalafande Che; Shakaff, Ali Yeon Md

doi:10.1109/iceese.2014.7154603

Cited by 14 publications

(2 citation statements)

References 31 publications

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“…1709 rich image processing areas, in which it is known as logarithmic image processing (LIP). The wide range of LIP implementation listed in [4]- [7] show the positive impact of logarithmic usage for image related implementation in DSP. Surprisingly, the operational speed for LNS could outperformed the FLP system for up to 50% [8]- [11].…”

Section: Introductionmentioning

confidence: 99%

Less memory and high accuracy logarithmic number system architecture for arithmetic operations

Naziri

Ismail

Isa

et al. 2021

IJEECS

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<p>Interpolation is another important procedure for logarithmic number system (LNS) addition and subtraction. As a medium of approximation, the interpolation procedure has an urgent need to be enhanced to increase the accuracy of the operation results. Previously, most of the interpolation procedures utilized the first degree interpolators with special error correction procedure which aim to eliminate additional embedded multiplications. However, the interpolation procedure for this research was elevated up to a second degree interpolation. Proper design process, investigation, and analysis were done for these interpolation configurations in positive region by standardizing the same co-transformation procedure, which is the extended range, second order co-transformation. Newton divided differences turned out to be the best interpolator for second degree implementation of LNS addition and subtraction, with the best-achieved BTFP rate of +0.4514 and reduction of memory consumption compared to the same arithmetic used in european logarithmic microprocessor (ELM) up to 51%.</p>

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Section: Introductionmentioning

confidence: 99%

Less memory and high accuracy logarithmic number system architecture for arithmetic operations

Naziri

Ismail

Isa

et al. 2021

IJEECS

Self Cite

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“…Traditional or reported multiplication was limiting performance in terms of accuracy as well as hardware overhead. Logarithm multiplier must have the potential to become an option of a traditional multiplier for real-time digital signal processor [14][15][16][17][18][19].…”

Section: Introductionmentioning

confidence: 99%

An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

Nandan¹

2020

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Digital Signal Processing (DSP) applications demand error-free and compact hardware architecture of arithmetic operations. A logarithmic operation provides an efficient option in place of binary arithmetic. In this paper, it is suggested that 11-region and 17-region error correction schemes for developing an efficient antilogarithm converter. It is used for developing the most accurate and compact logarithm multiplier which is used in the DSP processor. Implementations of reported and proposed designs are investigate based on accuracy and hardware overhead and it found outperform in comparisons of previously reported designs. The proposed 11-region converter involves 61% less Area Delay Product (ADP) and 49.82% less energy in comparisons of the reported 11-region antilogarithmic converter and 17-region converter involves 48.02% less ADP and 32.53% less energy in comparisons of the reported 14-region antilogarithmic converter. The proposed antilogarithmic converter achieves 1.697% and 1.084% error for 11-region and 17-region designs respectively than of reported designs of 1.876% and 1.351% for 11-region and 17region respectively.

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Optimization of the Hardware Costs of Interpolation Converters for Calculations in the Logarithmic Number System

Osinin¹

2019

Recent Research in Control Engineering and Decision Making

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The design revolution of logarithmic number system architecture

Cited by 14 publications

References 31 publications

Less memory and high accuracy logarithmic number system architecture for arithmetic operations

Less memory and high accuracy logarithmic number system architecture for arithmetic operations

An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

Optimization of the Hardware Costs of Interpolation Converters for Calculations in the Logarithmic Number System

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