The development of a macro-modeling tool to develop IBIS models

“…The generated surrogate IBIS model is compared to the reference provided by the transistor-level simulation, and to the traditional IBIS model extracted from SPICE using the S2IBIS3 v1.0 tool [16]. [12] The test setup is shown in Fig.…”

Section: Examplementioning

confidence: 99%

Model-Based Variation-Aware Integrated Circuit Design

Zhu

Yelten

Steer

et al. 2013

Surrogate-Based Modeling and Optimization

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Modern integrated circuit designers must deal with complex design and simulation problems while coping with large device to device parametric variations and often imperfect information. This chapter presents surrogate model-based methods to generate circuit performance models for design, device models, and highspeed input-output (IO) buffer macromodels. Circuit performance models are built with design parameters and parametric variations, and they can be used for fast and systematic design space exploration and yield analysis. Surrogate models of the main device characteristics are generated in order to assess the effects of variability in analog circuits. The variation-aware IO buffer macromodel integrates surrogate modeling and a physically based model structure. The new IO macromodel provides both good accuracy and scalability for signal integrity analysis.

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“…The fundamental limitation of IBIS is that the physical effects to be considered are decided a priori when the equivalent circuit is defined, leaving little or no possibility for including the effects inherent to the device [6]. IBIS models also fail to capture the dynamic characteristics of the driver accurately as the modeling technique relies primarily on static characteristics [5]. IBIS models lose accuracy when extended to multiple ports [6].…”

Section: Introductionmentioning

confidence: 99%

Macromodeling of Nonlinear Transistor-Level Receiver Circuits

Mutnury

Swaminthan

Cases³

et al. 2006

IEEE Trans. Adv. Packag.

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In this paper, a modeling methodology for macromodeling transistor-level receiver circuits has been presented. A few receiver modeling techniques have been proposed in the past, but these modeling techniques only address the loading effect of the receiver circuits, i.e., the input characteristics of the receivers. In this paper, a modeling methodology that addresses both the loading effect as well as the output characteristics of the receiver has been proposed. This modeling technique is simple, accurate, and has huge computational speed-up over transistor-level receiver circuits. To model the input characteristics of the receiver, spline function with finite time difference (SFWFTD) and recurrent neural network (RNN) modeling methods have been used. The output characteristics of the receiver are modeled using a combination of receiver static characteristics and a delay element that takes into account the timing delay of the receiver. The accuracy of the modeling approach has been tested on some test cases and results show good accuracy and substantial speed-up compare to transistor-level receiver circuits. The proposed modeling technique has been extended to multiple ports to estimate sensitive effects like simultaneous switching noise (SSN) when multiple receivers are switching.Index Terms-Artificial neural networks (ANNs), input/output buffer information specification (IBIS), macromodeling,, receiver circuits, recurrent neural networks (RNNs), simultaneous siwtching noise (SSN).

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The development of a macro-modeling tool to develop IBIS models

Cited by 18 publications

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Application of surrogate modeling to generate compact and PVT-sensitive IBIS models

Application of surrogate modeling to generate compact and PVT-sensitive IBIS models

Model-Based Variation-Aware Integrated Circuit Design

Macromodeling of Nonlinear Transistor-Level Receiver Circuits

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