The effect of a biased conductive mask on porous silicon formation

Abstract

Patterned macro porous p ‐type silicon has been produced using a conductive chromium and gold mask while the masking layers were electrically biased under a variety of conditions. The purpose of this work is to study the impact on pore formation near the mask edge by the modulation of the electric field orientation adjacent to the mask edge. The goal is to minimize the amount of lateral pore growth at the mask edge. The masking layers were biased at potentials between the anode and cathode potential during electrochemical anodization in an ethanoic hydrofluoric acid solution. Process conditions were defined to transfer a fraction of the total current from the sample substrate to the cathode, effectively controlling the current density in the mask, and control the electric field orientation near the mask edge. The mask bias impacted the etch rate and the profile of the pore growth at the mask edge. It was observed that if the mask was biased with respect to the anode, the impact on the porous silicon profile at the mask edge was greater than with other biasing configurations. It was observed also that the etch rate of the chromium masking layer was accelerated while biasing with respect to the cathode at a constant current density. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Optimized plasma-polymerized fluoropolymer mask for local porous silicon formation

“…In the literature, different kinds of HF resistant materials have been tested and proposed as a masking layer for deep PS formation. [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28] Among them, silicon nitride (Si x N y ), 15,16 bilayer of polycrystalline silicon/silicon dioxide, 18,22 or tri-layer stack of poly-Si/Si x N y /SiO 2 12 are the most widely used masking materials due to the maturities of deposition techniques and the compatibility with current silicon processing. However, the common drawback of all these masking materials is the complicated post-etching mask removal procedures when bare silicon surface is ultimately required.…”