The effect of employing advanced branching mechanisms in superscalar processors

Abstract

This paper discusses the effect of employing advanced branching mechanisms in superscalar processors. The motivation behind employing advanced branching mechanisms in superscalar processors is to reduce the control dependence, or in other words the number of branch operations, in the program so that instruction-level parallelism can be exploited more effectively. The second effect achieved by reducing the control dependence in the program is a decrease of the amount of branch penalty due to less branch operations. In this paper, two advanced branching mechanisms are discussed. The first mechanism involves incorporating multiple condition registers in superscalar processors. The second mechanism is a novel multi-way branching scheme proposed in this paper. A quantitative analysis on the effect of the two branching mechanisms shows that incorporating multiple condition registers can boost the superscalar processor performance by a factor of 16% to 20% while employing the proposed multi-way branching mechanism can achieve even greater performance improvement, up to 47%. 35

Branch merging for scheduling concurrent executions of branch operations

“…The system proposed in [12] also considered the combining of multiway branching with predicated execution. Multiway branching can be applied to superscalar processors as well [18]. The hardware now has to collect multiple branch operations, determine their priorities, and also check for possible dependencies.…”