The Effect of H2O2 and 2-MT on the Chemical Mechanical Polishing of Cobalt Adhesion Layer in Acid Slurry

A colloidal silica-based slurry (3-10 wt%) containing H 2 O 2 (1 wt%) and citric acid (50 mM) was found to polish chemical vapordeposited (CVD) cobalt (Co) films with removal rates (RRs) of ∼180-500 nm/min and a dissolution rate (DR) of ∼0 nm/min at pH 8 along with an RMS roughness of ∼0.5 nm and a corrosion current of ∼50 μA/cm 2 . Our results suggest that, in the presence of H 2 O 2 , the Co film surface was covered with a passive film of CoO in acidic conditions and Co 3 O 4 in alkaline conditions. However, in the presence of H 2 O 2 and citric acid in acidic conditions, formation of the soluble complex [Co(C 6 H 5 O 7 ) 2 ] 3− from abraded Co enhanced the RRs significantly. The roles of H 2 O 2 , citric acid, and silica abrasives as well as the pH on the Co material removal process are discussed and a removal mechanism is proposed. Two inhibitors namely, 1, 2, 4-Triazole (TAZ) and Benzotriazole (BTA), were tested in the presence of 50 mM citric acid at pH 8 but were found to be ineffective even at concentrations of 100 mM in reducing the E corr of Co-Ti couple to minimize galvanic corrosion that is essential when the Co/Ti structure is polished after the removal of bulk of Co and requires further study. Sub-10 nm devices face several challenges with copper as an interconnect material for back-end-of-the-line (BEOL) processes during the manufacture of integrated circuits. These include increasing resistivity with decreasing thickness, 1 non-conformal deposition at narrow trench widths ∼20 nm or less, 2 and scaling limitations of the diffusion barrier/liner.3 This led to the investigation of new trench filling materials. Cobalt is a promising alternative to meet the challenges of interconnect lines at these lower nodes for the first two metal layers M1 and M2, due to its lower resistivity at smaller dimensions (∼10 nm) compared to copper. [4][5][6] Kamineni et al. 7 proposed the use of chemical vapor deposited (CVD) cobalt to replace the widely used tungsten for local interconnects for 10 nm and smaller nodes. They emphasized two main advantages of CVD Co metallization which are a) CVD Co precursors do not damage the Ti liner enabling barrier scaling and b) it achieves void free fill in high aspect ratio features without defects, something that is difficult to achieve with a conventional physical vapor deposited (PVD) Co process. 8,9 Hence, CVD-based Co metallization is an attractive option for the technology nodes below 10 nm.CVD-based cobalt has also gained prominence in the advanced copper interconnects below 22 nm as liner [10][11][12][13][14][15][16][17] to improve adhesion between the barrier (TaN, TiN) and Cu seed layer where the Co film thickness is only ∼2 nm. Several authors 18-26 have investigated cobalt polishing for such applications where RR requirements are typically <20 nm/min and Co loss due to corrosion has to be as close to zero as possible, since even a minute loss of Co material can degrade the device reliability significantly. Hence, since the potential gap between Co and Cu is a large ∼0...

mentioning

confidence: 99%

Citric Acid as a Complexing Agent in Chemical Mechanical Polishing Slurries for Cobalt Films for Interconnect Applications

Popuri

Sagi

Alety

et al. 2017

“…In addition, Co structures must be polished at a sufficiently low (≤ 2 psi) down-pressure to avoid structural deformation of the underlying ultralow-k materials and to avoid erosion 17 ( Figure 1). Furthermore, during barrier polishing, galvanic corrosion 12,16,[18][19][20][21] can occur when electrochemically different materials are electrically connected and immersed in an electrolyte, as shown in Figure 2. The standard reduction potentials of Co/Co 2+ and Ti/Ti 2+ couples are −0.28 V and −1.63 V, respectively.…”

mentioning

confidence: 99%

Potassium Oleate as a Dissolution and Corrosion Inhibitor during Chemical Mechanical Planarization of Chemical Vapor Deposited Co Films for Interconnect Applications

Popuri

Amanapu

Ranaweera

et al. 2017

1,2-4 Triazole (TAZ), N-lauroylsarcosine sodium salt (NLS) and potassium oleate (PO) were tested as passivating additives to previously developed H 2 O 2 and citric acid-based silica dispersions for the polishing of chemical vapor deposited Co films for interconnect applications. In comparison to TAZ and NLS, Co corrosion currents are ∼1 to 2 order of magnitude lower (∼1-3 μA cm −2 ) at pH 7 with PO and post-polish surface quality was much better. The galvanic corrosion currents between Co-Ti and Ti-TiN couples with PO were also very low (∼0.1 μA cm −2 ), making the previously developed silica and citric acid-based dispersion, now containing PO, suitable for both bulk removal of Co (step I) and for planarizing Co/Ti/TiN structures (step II) with excellent selectivity while stopping on low-k dielectric. Langmuir adsorption isotherm model analysis showed that the standard free energies of adsorption values were ∼−40 kJ/mol for PO suggesting chemisorption. Fourier transform infra-red (FTIR) and attenuated FTIR spectroscopy data show bridging coordination between the carboxylate ligand of PO and the Co surface. Cobalt is being evaluated as a possible alternative to replace copper as an interconnect metal for 10 nm and smaller technology nodes.1-5 The fabrication of the interconnects starts with the formation of trenches in a low-k dielectric. Liner/barrier layer, typically Ti/TiN 6 , is then deposited, followed by the filling of the trenches with Co by physical vapor deposition (PVD), 7,8 chemical vapor deposition (CVD) 6 or electroplating (ECP), and then removing the metal overburden by chemical mechanical planarization (CMP). 9 To prevent damage to the underlying softer low-k structures, the polishing of the metal films has to be performed at low pressures (∼1-2 psi) requiring the chemical component of the CMP process to be more dominant. 10Typically, interconnect CMP is a two-step process.2 The first step involves removal of the overburden at ∼300 nm/min or more 11 till about 10-20 nm of it remains. Then, a second step removes the residual Co along with the underlying liner/barrier at a relatively slower rate of ∼20-50 nm/min 12,13 while, and more importantly, controlling the galvanic corrosion between Co-Ti (liner) and Ti-TiN (barrier) couples and achieving close to 1:1:1 removal rate (RR) selectivity for Co:Ti:TiN and stopping on the low-k dielectric.An important aspect of polishing the interconnects is to protect the recessed regions of the wafer surface from dissolution while the protruding areas are selectively planarized.14 Controlling dissolution during CMP minimizes dishing (Figure 1) and helps achieve effective planarization. It is known that Co corrodes very easily in aqueous solutions.15 For example, it was shown recently that pits were generated on the film surface even at neutral conditions of pH ∼7, when exposed to a mixture of H 2 O 2 and citric acid 9 caused by the soluble complexation reaction between CoO formed at the surface and the citrate ligands, creating localized cavities in the surface la...

“…Stabilized OCPs recorded in pH-varied slurries are useful to construct OCP-pH correlation charts, which can be mapped onto Pourbaix diagrams to categorize the CMP-specific primary surface species for a given test system. 22,23 Raman, optical absorption and X-ray photoelectron spectroscopies can be combined with MRR and electrochemical measurements 24,25 to further analyze the CMP specific surface species.…”

Section: Scopes Of Electrochemical Studies In Metal Cmp Researchmentioning

confidence: 99%

Perspective—Electrochemical Assessment of Slurry Formulations for Chemical Mechanical Planarization of Metals: Trends, Benefits and Challenges

Roy¹

2018

With continued shrinkage of circuit dimensions, the technique of chemical mechanical planarization (CMP) has become progressively more intricate through the last decade. Since the chemical mechanism of metal CMP is governed by electrochemical effects, the complex task of CMP-slurry engineering can be economically assisted in the electroanalytical approach by using laboratory scale model systems. This article discusses how CMP has been impacted by device scaling, and examines the status of fundamental studies of metal CMP. The techniques suitable for studying model CMP systems are discussed, along with an assessment of the utilities and the practical limits of such experiments. Chemical mechanical planarization (CMP) is an essential processing step of integrated circuit (IC) fabrication. 1,2 CMP of the metal components of logic devices constitute a major aspect of this technique and, like other areas of IC manufacturing, metal CMP has become quite complex while addressing the emerging demands of technology through the last decade. 3 The new challenges of metal CMP originate from both the scaling and the novel material aspects of these systems. 3,4 At the same time, published reports indicate that, many of these issues, especially those related to the slurry consumables, 5 can be addressed to a large extent through electroanalytical examinations of slurry functions using scaled down models of actual CMP systems. 6 Recent studies performed in industrial facilities have also identified a critical need to further advance the fundamental understanding of metal CMP. 7,8 The present article provides a perspective on these fundamental research aspects of metal CMP that are in the core of most laboratory scale studies of these systems. Device Scaling and CMP ConsiderationsThe International Technology Roadmap for Semiconductors (ITRS) specified the earlier technology nodes in terms of the DRAM half-pitch (hp), or the microprocessor's level-1 metal hp of a device. 9 Basically until the 65 nm node, the shrinkage of feature-size has continued in line with Dennard scaling, by a factor (S) of 1/ √ 2, to accommodate doubling of transistors per unit chip area (scaling as S 2 = 1/2) every two years in relation to Moore's law. 10 Increased leakage currents in the subsequent feature reductions have eventually shifted this technology trend, with the emergence of advanced multicore systems. 11 While the scaling factor of 1/ √ 2 has been largely maintained in the post-Dennard period, the newer logic devices have evolved in a more complex manner compared to their earlier counterparts. The middle-of-line (MOL) metallization scheme has emerged from the need to reduce the parasitic effects of active wiring that extends over 4 km cm −2 for >13 metal layers. 9 Novel diffusion barriers and ultra-low-k (ULK) dielectrics, Fin field effect transistors (Fin-FETs), high-k gate dielectrics, and exploratory designs/materials for local interconnects have been steadily incorporated in new device architectures in keeping with the advents of scaling sch...