The Effect of Operating Frequency in the Radiation Induced Buildup of Trapped Holes and Interface States in MOS Devices

Stanley, T.; Neamen, Donald A.; Dressendorfer, P. V.; Schwank, J.R.; Winokur, P.S.; Ackermann, Mark R.; Jungling, K. C.; Hawkins, C.F.; Grannemann, W. W.

doi:10.1109/tns.1985.4334054

Cited by 57 publications

(6 citation statements)

References 15 publications

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“…In integrated circuit applications, CMOS devices are clocked and switch bias states frequently. Thus, a more realistic bias condition features a clocked V in signal during TID exposure. − To explore this case, the fully recovered device previously featured in the V in dose LOW static bias case was further irradiated while biased under dynamic V in conditions. Figure a plots V in , V out , and the total dissipated power before, during, and after an additional accumulated dose of 1.2 Mrad.…”

Section: Results and Discussionmentioning

confidence: 99%

Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes

McMorrow¹,

Cress

Rojas³

et al. 2017

ACS Nano

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Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

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Section: Results and Discussionmentioning

confidence: 99%

Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes

McMorrow¹,

Cress

Rojas³

et al. 2017

ACS Nano

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“…First, it has been assumed that steady state conditions are maintained throughout the irradiation period, which may be unrealistic for many continuously-clocked systems. Since the MOS parameter shifts for non-steady-state operating conditions are always less than those obtained for the worst-case steady-state conditions [10], the method described above may provide an overlypessimistic radiation failure level prediction. The method can be extended to include the identification of sub-circuits which operate under non-steady-state conditions prior to the assignment of worst-case post-radiation parameters.…”

Section: Conclusion and Extensionsmentioning

confidence: 99%

Simulation of Worst-Case Total Dose Radiation Effects in CMOS VLSI Circuits

Bhuva¹,

Paulos²,

Diehl

1986

IEEE Trans. Nucl. Sci.

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A new methodology for evaluating worst-case radiation failure levels for CMOS VLSI circuits in total dose environments is presented. The new methodology reduces computation time by orders of magnitude by using simple calculations to identify vulnerable sub-circuits and worst-case irradiation and operating bias conditions. Sensitive sub-circuits are then analyzed by accurate, device-level simulators to predict radiation failure levels. The method has been implemented and results for sample circuits are described.

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“…The rays and particles in space may cause serious radiation damage to the semiconductor devices. Among all the radiation effects, the total ionizing dose (TID) effect plays an important role and has been investigated for decades of years [1][2][3][4][5][6][7][8]. The TID effect can affect the device performance by shifting the threshold voltage, lowering the transconductance, increasing the off-state leakage current and so on [9, lO].…”

Section: Introductionmentioning

confidence: 99%

Investigation on TID tolerance of 65nm bulk silicon nMOSFETs

Chen

et al. 2014

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

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The radiation response of 6Snm bulk silicon NMOSFETs is investigated, such as core devices and 110 devices. The results indicate that radiation induced threshold voltage (VT) shift is not evident for both types of devices. The degradation of the off-state leakage current of core devices is not significant, which illustrates weak dependence on device geometry. However, the off-state leakage current degradation of 110 transistors is relatively obvious which may have an impact on the static power consumption of integrated circuit. The results indicate that I/O devices may be paid more attention for radiation-hardened design.

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The Effect of Operating Frequency in the Radiation Induced Buildup of Trapped Holes and Interface States in MOS Devices

Cited by 57 publications

References 15 publications

Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes

Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes

Simulation of Worst-Case Total Dose Radiation Effects in CMOS VLSI Circuits

Investigation on TID tolerance of 65nm bulk silicon nMOSFETs

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