Ion Implantation Technology. 2002. Proceedings of the 14th International Conference On 2002
DOI: 10.1109/iit.2002.1257943
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The effect of sub-1000&amp;amp;deg;C source/drain anneal temperature on transistor in conventional SiO<sub>2</sub> integration and high-k dielectric integration

Jae Eun Lim1,
Yudong Kim Yudong Kim2,
K. Torres3
et al.
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