“…When the circuit connection was at configuration A, I A (1,1) >I A (1,0) ≈I A (0,1) >I A (0,0) . In the range of I A (1,1) >I >I A (1,0) , the device for only logic input (1,1) was at LRS (logic output=0), and for the other logic inputs of (0,0), (1,0) and (0,1) was at HRS (logic output=1), which represented the NAND logic operation. In the range of I A (1,0) >I >I A (0,0) , the device for only logic input (0,0) was at HRS (logic output=1), and for the other logic inputs of (1,1), (1,0) and (0,1) was at LRS (logic output=0), which represented the NOR logic operation.…”