The Entropy of FPGA Reconfiguration

Abstract

In line with Shannon's ideas, we define the entropy of FPGA reconfiguration to be the amount of information needed to configure a given circuit onto a given device. We propose using entropy as a gauge of the maximum configuration compression that can be achieved and determine the entropy of a set of 24 benchmark circuits for the Virtex device family. We demonstrate that simple off-the-shelf compression techniques such as Golomb encoding and hierarchical vector compression achieve compression results that are within 1-10% of the theoretical bound. We present an enhanced configuration memory system based on the hierarchical vector compression technique that accelerates reconfiguration in proportion to the amount of compression achieved. The proposed system demands little additional chip area and can be clocked at the same rate as the Virtex configuration clock.

Post-Placement Interconnect Entropy

“…Approaches like AMBA [1], CoreConnect [2], WISHBONE [3], and SiliconBackplane [4] follow a shared bus scheme that works well for master-slave communication patterns, where there are only a few masters. When there are several masters (e.g., processors) in the system, synchronization, data interchange, and input/output (I/O) may saturate the bus and contention will slow down data transfers.…”

“…But here we are concerned with the entropy, which may be thought of as the smallest possible number of bits allowing unlimited decoding logic. The entropy of a complete programmable interconnect may be thought of as the length of the optimally compressed bit string needed to program it [4]. (We consider only those bits needed to configure the interconnect itself, not any additional bits to configure the logic cells.)…”