The essence of Bluespec: a core language for rule-based hardware design

Abstract

The Bluespec hardware-description language presents a significantly higher-level view than hardware engineers are used to, exposing a simpler concurrency model that promotes formal proof, without compromising on performance of compiled circuits. Unfortunately, the cost model of Bluespec has been unclear, with performance details depending on a mix of user hints and opaque static analysis of potential concurrency conflicts within a design. In this paper we present Kôika, a derivative of Bluespec that preserves its desirable properties and yet gives direct control over the scheduling decisions that determine performance. Kôika has a novel and deterministic operational semantics that uses dynamic analysis to avoid concurrency anomalies. Our implementation includes Coq definitions of syntax, semantics, key metatheorems, and a verified compiler to circuits. We argue that most of the extra circuitry required for dynamic analysis can be eliminated by compile-time BSV-style static analysis.CCS Concepts: • Software and its engineering → Semantics; Compilers; • Hardware → Theorem proving and SAT solving.

Coq’s vibrant ecosystem for verification engineering (invited talk)

“…And you will want a tool for proving that the circuit design implements your functional model: Kôika 14 [15] is a Coq formalization of Bluespec-a Haskelllike functional language for describing digital circuits.…”

Hemiola: A DSL and Verification Tools to Guide Design and Proof of Hierarchical Cache-Coherence Protocols

“…The parent, at this moment, changes its directory status to a transient state to disallow any other requests from the children (e.g., f rqM), since otherwise it will handle two rqM messages simultaneously, which might lead to an incoherent state -two M statuses in the caches. Lastly, 4 shows the case that C 2 handles the invalidation request ( c rqI). A number of corner cases should be handled carefully in this step:…”

Formal verification of high-level synthesis

“…Verilog was chosen as the output language for Vericert because it is one of the most popular HDLs and there already exist a few formal semantics for it that could be used as a target Meredith et al 2010]. Bluespec, previously ruled out as a source language, is another possible target and there exists a formally verified translation to circuits using Kôika [Bourgeat et al 2020].…”

“…12, which is represented as an Euler diagram. The categories chosen for the Euler diagram are: whether the tool is usable, whether it takes a Standard HLS tools [Canis et al 2011;Intel 2020b] [Nigam et al 2020Xilinx 2020] Translation validation approaches [Clarke et al 2003;Kundu et al 2008;Mentor 2020] Vericert Kôika [Bourgeat et al 2020] Lööw [2021] Ellis [2008] Perna and Woodcock [2012] BEDROC [Chapman et al 1992] Correctness proof…”