1997
DOI: 10.1149/1.1837912
|View full text |Cite
|
Sign up to set email alerts
|

The Evolution of (001) Si / SiO2 Interface Roughness during Thermal Oxidation

Abstract: In this work, w e first demonstrate the interface roughness as a function o f oxide thickness. For intentionally roughened samples, interface roughness always decreases as oxide thickness increases. O n the other hand, samples only treated with a regular preoxidation clean show a different quantitative trend. For such samples, the interface is initially roughened, and then becomes smooth as oxide thickness increases. This implies that the evolution o f interface roughness depends on h o w samples are pre ared … Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
8
0

Year Published

1999
1999
2021
2021

Publication Types

Select...
6
1
1

Relationship

0
8

Authors

Journals

citations
Cited by 28 publications
(8 citation statements)
references
References 5 publications
0
8
0
Order By: Relevance
“…Here the spread of the interface is defined as the distance between the Si 0.71 Ge 0.29 and Si 0.99 Ge 0.01 points. The spread of the interface after annealing at 1000 C is substantially worse than the rms roughness measured on Si/SiO 2 interfaces [71] of only 0.3 nm for thin oxides. As annealing at 1000 C for many minutes is common in many CMOS processes, care has to be taken in designing annealing processes that do not degrade the heterointerfaces if Si 1±x Ge x is to be processed using CMOS techniques.…”
Section: Applications Using Virtual Substratesmentioning
confidence: 66%
“…Here the spread of the interface is defined as the distance between the Si 0.71 Ge 0.29 and Si 0.99 Ge 0.01 points. The spread of the interface after annealing at 1000 C is substantially worse than the rms roughness measured on Si/SiO 2 interfaces [71] of only 0.3 nm for thin oxides. As annealing at 1000 C for many minutes is common in many CMOS processes, care has to be taken in designing annealing processes that do not degrade the heterointerfaces if Si 1±x Ge x is to be processed using CMOS techniques.…”
Section: Applications Using Virtual Substratesmentioning
confidence: 66%
“…It is indeed possible to study desorption kinetics with a more stable thermally grown SiO 2 film on MC surface. However, any potential experiment intending to grow SiO 2 on MC will alter the surface morphology and may introduce the residual intrinsic stress [20][21][22], which will influence the desorption kinetics.…”
Section: Methodsmentioning
confidence: 99%
“…The dry oxidation is carried out for 3 min at a temperature of 1100 • C, i.e., higher than the viscous flow point. Although such a high temperature prevents a self-limiting oxidation [15], it allows transforming the cross section of the SiNW from triangular to a circular shape while minimizing the degradation of the Si-SiO 2 interface due to roughness induced by the oxidation process [16]. Next, etch windows are patterned in source/drain contact areas and opened up by removing the oxide shell with buffered oxide etch (BOE).…”
Section: Device Fabricationmentioning
confidence: 99%
“…In order to elaborate further on the behavior of RFETs and in particular to understand the difference in the nonlinear behavior of the PGAD and PGAS operation modes, self-consistent device simulations using the nonequilibrium Green's function (NEGF) approach on a finite-difference grid have been carried out [22]. An effective mass approximation with symmetric conduction and valence band is assumed; the complex band structure within the bandgap is considered with Flietner's dispersion relation [23].…”
Section: Device Simulationsmentioning
confidence: 99%