The evolution of standard cell libraries for future technology nodes

Abstract

Evolvable Hardware has been a discipline for over 15 years. Its application has ranged from simple circuit design to antenna design. However, research in the field has often been criticised for not addressing real world problems. Intrinsic variability has been recognised as one of the major challenges facing the semiconductor industry. This paper describes an approach that optimises designs within a standard cell library by altering the transistor dimensions. The proposed approach uses a Multi-objective Genetic Algorithm to optimise the device widths within a standard cell. The designs are analysed using statistically enhanced transistor models (based on 3D-atomistic simulations) and statistical SPICE simulations. The goal is to extract high-speed and low-power designs, which are more tolerant to the random fluctuations present in current and future technology nodes. The results

On area minimization of complex combinational circuits using cartesian genetic programming

“…This seminal work has been extended in several ways. The most recent research in the area of digital circuits includes the evolution of novel standard cell libraries for future tech nology nodes [3] and a post synthesis optimization of complex combinational circuits using formal verification principles [4]. While the achievable quality of resulting design/optimization is usually very high, the computational time required to achieve that result is the main drawback.…”

Exploiting the reconfigurability of the PAnDA architecture to overcome physical substrate variations

“…Most severely affected designs are SRAMs and latches, which are fundamental elements of any current programmable logic architecture. The results in [5], [16], [17], which have been obtained from statistical SPICE simulations, suggest that optimising the widths of transistors in standard cells can improve their variability tolerance, speed and power consumption. It has been also shown that it is possible to design and optimise analogue CMOS circuits in hardware using field programmable transistor arrays (FPTAs) [14], [18].…”

“…It has been also shown that it is possible to design and optimise analogue CMOS circuits in hardware using field programmable transistor arrays (FPTAs) [14], [18]. Therefore, if FPTA based mechanisms to alter device sizes according to [5] could be incorporated in hardware, it would be possible to optimise designs post fabrication in a dynamic fashion. This would not only have the advantage of being able to enhance variability tolerance and performance for a specific design, but could also account for variations between different devices.…”

“…Unfortunately, due to the statistical nature of the variations, the fabrication yield still decreases while failure rates increase significantly, because every physical instance of a design behaves in a stochastically different manner [2]- [4]. Even when verifying designs using accurate device models and statistical SPICE simulation, this will in the first instance only allow for a more accurate yield prediction, rather than overcome the effects of random variability, unless the additional information gained can be successfully used to improve the designs [5]. However, this is a highly complex task and it is not straight forward to decide how to change circuit topologies and device sizes in order to improve the performance of a large design or bringing it back into specification.…”

Circuit design optimisation using a modified genetic algorithm and device layout motifs

“…The circuit topology and functionality optimisation can be considered as a combinatorial optimisation problem. The ability of evolutionary algorithms to handle combinatorial optimisation problems using genetic algorithm makes them an interesting candidate to solve this problem [8]- [11]. This paper, for the first time, develops a comprehensive methodology to extract device and circuit parameters (including variability information) from motif structures, and uses these parameters in an EA driven circuit simulator to optimise standard cells through an evolutionary algorithm.…”