The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping

Mueller-Gritschneder, Daniel; Devarajegowda, Keerthikumara; Dittrich, Martin; Ecker, Wolfgang; Greim, Marc; Schlichtmann, Ulf

doi:10.1145/3130265.3138858

Cited by 19 publications

(3 citation statements)

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“…Too much customization can lead to the point, that SW incompatibilities between RISC-V implementations are introduced which in turn cause fragmentation of the ecosystem. This crucial problem has been recognized by the RISC-V foundation and therefore the compliance task group has been formed to develop efficient methods for compliance testing 26) . In contrast to design verification, which attempts to find bugs in the processor and ultimately prove correctness of the full functional behavior, compliance testing focuses on checking the relevant parts for the HW/SW interface to ensure compatibility of the processor with the RISC-V SW ecosystem.…”

Section: Motivation On Compliance Testing For Risc-vmentioning

confidence: 99%

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Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges

Herdt

Drechsler

2021

Sci. China Inf. Sci.

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Virtual prototypes (VPs) are crucial in today’s design flow. VPs are predominantly created in SystemC transaction-level modeling (TLM) and are leveraged for early software development and other system-level use cases. Recently, virtual prototyping has been introduced for the emerging RISC-V instruction set architecture (ISA) and become an important piece of the growing RISC-V ecosystem. In this paper, we present enhanced virtual prototyping solutions tailored for RISC-V. The foundation is an advanced open source RISC-V VP implemented in SystemC TLM and designed as a configurable and extensible platform. It scales from small bare-metal systems to large multi-core systems that run applications on top of the Linux operating system. Based on the RISC-V VP, this paper also discusses advanced VP-based verification approaches and open challenges. In combination, we provide for the first time an integrated and unified overview and perspective on advanced virtual prototyping for RISC-V.

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Section: Motivation On Compliance Testing For Risc-vmentioning

confidence: 99%

“…A few approaches have been designed to work in combination with SystemC. ETISS [26] 10) is a configurable ISS that provides RISC-V support, leverages DBT to achieve a high performance and is implemented in C++. ETISS can be used standalone or integrated with a SystemC-based simulation.…”

Section: Introductionmentioning

confidence: 99%

Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges

Herdt

Drechsler

2021

Sci. China Inf. Sci.

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“…The Extensible Translating Instruction Set Simulator (ETISS) focuses on extensibility [34] to support fast prototyping. As ETISS already supports the standard RISC-V base instruction sets, contains a virtual prototype of the PULPino [21] SoC, and allows profiling the application execution time, the use of this simulator was a natural decision our binarized image classifier application.…”

Section: A the Etiss Simulatormentioning

confidence: 99%