The fabrication of a double-layer atom chip with through silicon vias for an ultra-high-vacuum cell

Abstract

This study presents a double-layer atom chip that provides users with increased diversity in the design of the wire patterns and flexibility in the design of the magnetic field. It is more convenient for use in atomic physics experiments. A negative photoresist, SU-8, was used as the insulating layer between the upper and bottom copper wires. The electrical measurement results show that the upper and bottom wires with a width of 100 µm can sustain a 6 A current without burnout. Another focus of this study is the double-layer atom chips integrated with the through silicon via (TSV) technique, and anodically bonded to a Pyrex glass cell, which makes it a desired vacuum chamber for atomic physics experiments. Thus, the bonded glass cell not only significantly reduces the overall size of the ultra-high-vacuum (UHV) chamber but also conducts the high current from the backside to the front side of the atom chip via the TSV under UHV (9.5 × 10−10 Torr). The TSVs with a diameter of 70 µm were etched through by the inductively coupled plasma ion etching and filled by the bottom-up copper electroplating method. During the anodic bonding process, the electroplated copper wires and TSVs on atom chips also need to pass the examination of the required bonding temperature of 250 °C, under an applied voltage of 1000 V. Finally, the UHV test of the double-layer atom chips with TSVs at room temperature can be reached at 9.5 × 10−10 Torr, thus satisfying the requirements of atomic physics experiments under an UHV environment.

Fifteen years of cold matter on the atom chip: promise, realizations, and prospects

“…As three-dimensional (3D) fabrication becomes more common, substrates allowing high aspect-ratio etching are also required. Tasks include etching channels for conductors in multi-layer chips, vias for back-side electrical contacts [ 195 ] and holes for loading atoms or ions from the back side. More elaborate tasks include vacuum chambers embedded within the substrate.…”

“…For specific applications one requires additional features such as low tangent loss for chips with high-frequency radiation (e.g., ion chips). Substrates should have the right crystal unit structure and thermal expansion coefficient to accommodate unique materials (e.g., superconductors) and be strong enough for use as a facet of the vacuum chamber, in which case through-wafer etchings (vias) should also be vacuum compatible [195]. Substrates should also be able to easily accommodate multi-layer chip designs [171,196,197].…”

Laser drilling of via micro-holes in single-crystal semiconductor substrates using a 1070nm fibre laser with millisecond pulse widths

“…Via electrical interconnects have particular application in environments where compactness and low weight are at a premium, such as in space applications. Further applications are the manufacture of uniformly sized holes for the introduction of vapour fluxes and such holes and interconnects find application in quantum sensors such as ultra-cold atom experiments and ion trapping experiments [3]. The material removal mechanism is known to depend on the pulse length, with short pulses, i.e.…”

An investigation of supercritical-CO2copper electroplating parameters for application in TSV chips

“…The commonly encountered TSV fabrication methods consist of traditional electrodeposition method, which uses electroplating of metal with addition of surfactants to fill the TSV and achieve a satisfactory result [2,3]. But this kind of process will lead to a high impurity [4] content on the electrolyte and therefore on the TSV as well.…”