The Fast Discrete Periodic Radon Transform for prime sized images: Algorithm, architecture, and VLSI/FPGA implementation

2014 IEEE International Conference on Image Processing (ICIP)

2014

Self Cite

The Discrete Periodic Radon Transform (DPRT) has many important applications in image processing that are associated with reconstructing objects from projections (e.g., computed tomography [1]) or image restoration (e.g., [2]). Thus, there is strong interest in the development of fast algorithms and architectures for computing the DPRT.This paper introduces a scalable hardware architecture and associated algorithm for computing the DPRT for primesized images. For square images of size N × N , N prime, the DPRT requires N 2 (N − 1) additions for calculating image projections along a minimal number of prime directions. The proposed approach can compute the DPRT in N/2 h N + 2N + h clock cycles, h = 1, . . . , log 2 N , where h is a scaling factor that is used to control the required hardware resources that are needed to implement the fast DPRT. Compared to previous approaches, a fundamental contribution of the proposed architecture is that it allows effective implementations based on different constraints on the resources.

Section: Introductionmentioning

confidence: 61%

Section: Resultsmentioning

confidence: 94%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A scalable architecture for implementing the fast discrete periodic radon transform for prime sized images

2014 IEEE International Conference on Image Processing (ICIP)

2014

Self Cite

“…This manuscript introduces a fast and scalable approach for computing the forward and inverse DPRT that is based on parallel shift and add operations. Preliminary results were presented in conference publications in [26], [27]. The conference paper implementations were focused on special cases of the full system discussed here, required an external system to add the partial sums, assumed pre-existing hardware for transpositions, and worked with image strip-sizes that were limited to powers of two.…”

Section: Arxiv:211213149v1 [Csar] 24 Dec 2021mentioning

confidence: 99%

Fast and Scalable Computation of the Forward and Inverse Discrete Periodic Radon Transform

IEEE Trans. on Image Process.

2016

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The discrete periodic radon transform (DPRT) has extensively been used in applications that involve image reconstructions from projections. Beyond classic applications, the DPRT can also be used to compute fast convolutions that avoids the use of floating-point arithmetic associated with the use of the fast Fourier transform. Unfortunately, the use of the DPRT has been limited by the need to compute a large number of additions and the need for a large number of memory accesses. This paper introduces a fast and scalable approach for computing the forward and inverse DPRT that is based on the use of: a parallel array of fixed-point adder trees; circular shift registers to remove the need for accessing external memory components when selecting the input data for the adder trees; an image block-based approach to DPRT computation that can fit the proposed architecture to available resources; and fast transpositions that are computed in one or a few clock cycles that do not depend on the size of the input image. As a result, for an N × N image (N prime), the proposed approach can compute up to N(2) additions per clock cycle. Compared with the previous approaches, the scalable approach provides the fastest known implementations for different amounts of computational resources. For example, for a 251×251 image, for approximately 25% fewer flip-flops than required for a systolic implementation, we have that the scalable DPRT is computed 36 times faster. For the fastest case, we introduce optimized just 2N + ⌈log(2) N⌉ + 1 and 2N + 3 ⌈log(2) N⌉ + B + 2 cycles, architectures that can compute the DPRT and its inverse in respectively, where B is the number of bits used to represent each input pixel. On the other hand, the scalable DPRT approach requires more 1-b additions than for the systolic implementation and provides a tradeoff between speed and additional 1-b additions. All of the proposed DPRT architectures were implemented in VHSIC Hardware Description Language (VHDL) and validated using an Field-Programmable Gate Array (FPGA) implementation.

Fast 2D Convolutions and Cross-Correlations Using Scalable Architectures

IEEE Trans. on Image Process.

2017

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The manuscript describes fast and scalable architectures and associated algorithms for computing convolutions and cross-correlations. The basic idea is to map 2D convolutions and cross-correlations to a collection of 1D convolutions and cross-correlations in the transform domain. This is accomplished through the use of the discrete periodic radon transform for general kernels and the use of singular value decomposition -LU decompositions for low-rank kernels. The approach uses scalable architectures that can be fitted into modern FPGA and Zynq-SOC devices. Based on different types of available resources, for P×P blocks, 2D convolutions and cross-correlations can be computed in just O(P) clock cycles up to O(P) clock cycles. Thus, there is a trade-off between performance and required numbers and types of resources. We provide implementations of the proposed architectures using modern programmable devices (Virtex-7 and Zynq-SOC). Based on the amounts and types of required resources, we show that the proposed approaches significantly outperform current methods.