The feasibility of using image parameters for test pattern selection during OPC model calibration

Abdo, Amr Y.; Viswanathan, Ramya

doi:10.1117/12.846686

Cited by 12 publications

(5 citation statements)

References 10 publications

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“…In the work of Viehoever et al [3] they also use a k-means clustering approach, combining image parameter features and testing it in an artificial dataset only. Unfortunately, it has been shown in [1] that solely using image parameters is insufficient to compose an accurate sample plan. The authors start from an existing manually selected sample plan and manually reduce its size while making sure it still spans the image parameter space.…”

Section: State Of the Artmentioning

confidence: 99%

“…Of course the selection of patterns impacts the quality of models according to typical metrics such as cumulative critical dimension (CD) error across a verification set. Current practice involves a combination of engineering judgment and bucketing methods to insure that chosen samples cover bins in image parameter space, which is time-consuming and prone to over-fitting ( [1], [2]). Moreover, to ensure early market entry and better data coverage, turn-around time is becoming more critical.…”

Section: Introductionmentioning

confidence: 99%

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Automated sample plan selection for OPC modeling

et al. 2014

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It is desired to reduce the time required to produce metrology data for calibration of Optical Proximity Correction (OPC) models and also maintain or improve the quality of the data collected with regard to how well that data represents the types of patterns that occur in real circuit designs. Previous work based on clustering in geometry and/or image parameter space has shown some benefit over strictly manual or intuitive selection, but leads to arbitrary pattern exclusion or selection which may not be the best representation of the product. Forming the pattern selection as an optimization problem, which co-optimizes a number of objective functions reflecting modelers' insight and expertise, has shown to produce models with equivalent quality to the traditional plan of record (POR) set but in a less time.

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Section: State Of the Artmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Automated sample plan selection for OPC modeling

et al. 2014

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“…Several workers have reported on the benefit of ensuring a full range of aerial image parameters in the test suite. 28,29 Each technology node demands greater accuracy at smaller CD which at fixed NA and wavelength means lower Rayleigh k 1 factor, and as a result the number of distinct test patterns required to train a robust model has steadily increased. Additionally, the number of process conditions (dose and focus) at which calibration data must be collected has increased.…”

Section: Metrology and Model Calibrationmentioning

confidence: 99%

Challenges for patterning process models applied to large scale

Sturtevant

2012

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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Full-chip patterning simulation has been utilized in semiconductor manufacturing for more than ten years, and has been a key enabler for multiple technology generations, from 130 nm to the emerging 14 nm node. This span has featured two wavelength changes, a progression of optical NA increases (and a subsequent decrease), and a variety of patterning processes and chemistries. Full-chip patterning simulations utilize quasirigorous optical models and semiempirical resist and etch process models. There has been steady improvement in the predictive power and computational efficiency of the patterning models used in full chip simulation tools, and this paper will review this progress as well as the factors that ultimately limit the predictive capability of such models. In addition, this paper will outline the new process simulation challenges that are emerging as the industry approaches sub-0.25 k1 patterning. These challenges lie principally in improving accuracy and predictive capability, including 3D effects, for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.

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“…The Variable Threshold Resist Model (VTRM) and CM1 model are numerical fitting models using the aerial image as the input to predict the contour of ADI data [1][2][3] . The image parameter space (IPS) is an important metric characterizing the lithographic properties of a specific layout [4][5][6][7] . In the model calibration, image parameters play a key role.…”

Section: Introductionmentioning

confidence: 99%

Test pattern generation by conditional generative model labeled by image parameters

Qi,

Xu,

et al. 2024

DTCO and Computational Patterning III

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Test pattern generation plays a vital role in the model calibration in the optical proximity correction process. Traditional OPC resist models mainly use the image parameters such as the minimum intensity, the maximum intensity, the slope of intensity along the cut lines crossing the gauge points as their input parameters to calculate the resist contour position. To guarantee the accuracy of the resist model over the whole design layout, it is important that the image parameter space of the test patterns used to calibrate the OPC model covers the image parameter space of the original design layout. We present a method to generate test patterns based on the provided image parameters. The method is based on the adversarial neural network. With this method, we can prepare the test patterns with the desired image parameter coverage.

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The feasibility of using image parameters for test pattern selection during OPC model calibration

Cited by 12 publications

References 10 publications

Automated sample plan selection for OPC modeling

Automated sample plan selection for OPC modeling

Challenges for patterning process models applied to large scale

Test pattern generation by conditional generative model labeled by image parameters

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