2008
DOI: 10.1016/j.nima.2008.03.095
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The first version buffered large analog bandwidth (BLAB1) ASIC for high luminosity collider and extensive radio neutrino detectors

Abstract: Future detectors for high luminosity particle identification and ultra high energy neutrino observation would benefit from a digitizer capable of recording sensor signals with high analog bandwidth and large record depth, in a cost-effective, compact and low-power way.A first version of the Buffered Large Analog Bandwidth (BLAB1) ASIC has been designed based upon the lessons learned from the development of the Large Analog Bandwidth Recorder and Digitizer with Ordered Readout (LABRADOR) ASIC. While this LABRAD… Show more

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Cited by 43 publications
(19 citation statements)
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“…Using a variant of third-generation Buffered Large Analog Bandwidth (BLAB) ASICs [7], the waveforms are continuously sampled into a Switched-Capacitor Array (SCA) that has ∼ 10 µs of analog memory. When a trigger comes from the Belle II Global Decision Logic (GDL), the ASIC looks back in analog memory and digitizes the region of interest corresponding to the time of the event that caused the trigger.…”
Section: Hardwarementioning
confidence: 99%
“…Using a variant of third-generation Buffered Large Analog Bandwidth (BLAB) ASICs [7], the waveforms are continuously sampled into a Switched-Capacitor Array (SCA) that has ∼ 10 µs of analog memory. When a trigger comes from the Belle II Global Decision Logic (GDL), the ASIC looks back in analog memory and digitizes the region of interest corresponding to the time of the event that caused the trigger.…”
Section: Hardwarementioning
confidence: 99%
“…However, as a feasibility exercise, we have a strawman circuit that is based upon previous ASIC designs of ours (U. Hawaii) [17][18][19][20] shown schematically in Fig. 15.…”
Section: Strawman Designmentioning
confidence: 99%
“…By using this proportionality, the sampling interval can be determined individually from the differential amplitude for all the capacitor cells. Currently, several high-speed waveform sampling ASICs [7][8][9] based on the switched-capacitor cell technology are available in addition to the DRS4, and several time calibration methods developed for those ASICs have been reported in the literature [9][10][11][12]. Among them, the method [10] by Breton et al is similar to our approach: the sampling interval is extracted from a segment of a sine wave around a zero-crossing point while assuming linearity of the sine wave in the segment.…”
Section: Introductionmentioning
confidence: 99%